Calibration substrate

• US 7,994,803 B2
• Filed: 09/29/2009
• Issued: 08/09/2011
• Est. Priority Date: 07/09/2004
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Primary Examiner(s): Nguyen; Vinh P
• Application Number:
  US12/569,584
• Publication Number:
  US 20100017662A1
• Time in Patent Office: 679 Days
• Field of Search: None
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

A calibration substrate includes a plurality of input terminals, a detector coupled to the input terminals, and an output terminal. The calibration substrate can be used for calibrating and/or deskewing communications channels.

Claims

1. A calibration substrate for use in calibrating/deskewing drive channels of a machine, said machine having a plurality of first drive channels and a compare channel, said calibration substrate comprising:

a plurality of first input terminals disposed to receive input from said plurality of first drive channels;

a first buffer, wherein said first input terminals are electrically connected to an input of said first buffer;

a first detector configured to receive as input an output of said first buffer; and

a first output terminal electrically connected to an output of said first detector and configured to connect electrically with said compare channel.

2. The calibration substrate of claim 1, wherein said machine comprises a plurality of first compare channels, said calibration substrate further comprising a plurality of additional first output terminals each electrically connected to said input of said first buffer and configured to connect electrically with said plurality of first compare channels.

3. The calibration substrate of claim 2, wherein said machine comprises a plurality of second drive channels and a second compare channel, said calibration substrate further comprising:

a plurality of second input terminals disposed to receive input from said plurality of second drive channels;

a second buffer, wherein said second input terminals are electrically connected to an input of said second buffer;

a second detector configured to receive as input an output of said second buffer; and

a second output terminal electrically connected to an output of said second detector and configure to connect electrically to said second compare channel.

4. The calibration substrate of claim 3, wherein said machine comprises a plurality of second compare channels, said calibration substrate further comprising a plurality of additional second output terminals each electrically connected to said output of said second buffer and configured to connect electrically to said plurality of second compare channels.

5. The calibration substrate of claim 1, wherein electrical paths connecting said first input terminals to said input of said first buffer are of equal length.

6. The calibration substrate of claim 1 further comprising a plurality of resistors disposed between said first input terminals and said input of said first buffer.

7. The calibration substrate of claim 6, wherein said resistors are sized and disposed to match an impedance of said drive channels.

8. The calibration substrate of claim 1 further comprising an electronic filter disposed to filter said output of said first buffer.

9. The calibration substrate of claim 1, wherein said machine is a tester.

10. A calibration substrate for use in calibrating/deskewing a tester with a probe card assembly, said probe card assembly having a plurality of probes, said calibration substrate comprising:

a substrate;

a plurality of input terminals disposed on a same surface of said substrate and arranged in position to be contacted by said plurality of probes;

a summing node, wherein each of said input terminals are electrically connected to said summing node;

a detector having an input and an output, said input connected to said summing junction, said detector configured to detect a composite pulse feature of a composite pulse created at said summing junction; and

an output terminal disposed on said surface and electrically connected to said output of said detector and arranged in position to be contaced by a probe of said probe card assembly.

11. The calibration substrate of claim 10, wherein electrical paths connecting said input terminals to said summing junction are of equal length.

12. The calibration substrate of claim 10 further comprising a plurality of resistors disposed between said input terminals and said summing junction.

13. The calibration substrate of claim 10 further comprising a buffer disposed between said summing junction and said detector.

14. The calibration substrate of claim 10 further comprising an electronic filter disposed between said detector and said output terminal.

15. The calibration substrate of claim 10 wherein said detector is a power detector.

16. The calibration substrate of claim 10, wherein said detector is a pulse width detector.

17. The calibration substrate of claim 10, wherein said detector is a pulse slope detector.

18. The calibration substrate of claim 10, wherein said detector comprises any of:

a power detector, a pulse width detector, and a pulse slope detector.