Level shifter circuits and methods

• US 7,994,821 B1
• Filed: 04/02/2010
• Issued: 08/09/2011
• Est. Priority Date: 04/02/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Sung, Chiakang, Wang, Xiaobao, Nguyen, Khai
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): RICHARDSON, JANY
• Application Number:
  US12/753,389
• Time in Patent Office: 494 Days
• Field of Search: 326 62- 63, 326/68, 326 80- 83, 326 86- 87, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 3/356069 using additional transistors in the feedback circuit H03K3/356104, H03K3/3562 take precedence

Abstract

A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.

Claims

1. A level shifter circuit comprising:

first and second transistors, wherein the first transistor is directly coupled to the second transistor at a first node;

third and fourth transistors coupled in series, wherein the fourth transistor is coupled to the first node;

fifth and sixth transistors, wherein the fifth transistor is directly coupled to the sixth transistor at a second node; and

seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to the second node, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, and wherein the second input signal is inverted relative to the first input signal.

2. The level shifter circuit of claim 1 further comprising:

a ninth transistor coupled in series with the second transistor, wherein the ninth transistor receives the first input signal at a fifth control input; and

a tenth transistor coupled in series with the sixth transistor, wherein the tenth transistor receives the second input signal at a sixth control input.

3. The level shifter circuit of claim 1, wherein a terminal of each of the first and the fifth transistors is at a first supply voltage, and wherein a terminal of each of the third and the seventh transistors is at a second supply voltage that is less than the first supply voltage.

4. The level shifter circuit of claim 3 further comprising:

a ninth transistor coupled between the second transistor and a node at a ground voltage, wherein the ninth transistor receives the first input signal at a fifth control input; and

a tenth transistor coupled between the sixth transistor and a node at the ground voltage, wherein the tenth transistor receives the second input signal at a sixth control input.

5. The level shifter circuit of claim 1, wherein the fourth transistor is directly coupled to the first node, and wherein the eighth transistor is directly coupled to the second node.

6. The level shifter circuit of claim 1, wherein the level shifter circuit generates a level shifted output signal at the first node between the first and the second transistors in response to the first and the second input signals.

7. The level shifter circuit of claim 1, wherein the level shifter circuit is in a field programmable gate array integrated circuit.

8. A level shifter circuit comprising:

first and second transistors coupled in series;

third and fourth transistors coupled in series, wherein the fourth transistor is coupled to a first node between the first and the second transistors;

fifth and sixth transistors coupled in series; and

seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to a second node between the fifth and the sixth transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, wherein the third transistor receives the first input signal at a fifth control input, and wherein the seventh transistor receives the second input signal at a sixth control input.

9. The level shifter circuit of claim 8, wherein the first and the fifth transistors are cross-coupled, wherein a drain of the first transistor is directly coupled to a drain of the second transistor, and wherein a drain of the fifth transistor is directly coupled to a drain of the sixth transistor.

10. A level shifter circuit comprising:

first and second transistors coupled in series;

third and fourth transistors coupled in series, wherein the fourth transistor is coupled to a first node between the first and the second transistors;

fifth and sixth transistors coupled in series; and

seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to a second node between the fifth and the sixth transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, and wherein each of the third, the seventh, the ninth, and the tenth transistors has a thinner oxide thickness than each of the first, the second, the fourth, the fifth, the sixth, and the eighth transistors.

11. A level shifter circuit comprising:

a first transistor coupled to a node at a first supply voltage;

a second transistor coupled to the first transistor;

a third transistor coupled to a node at a second supply voltage;

a fourth transistor coupled to the third transistor, wherein the fourth transistor is directly coupled to each of the first and the second transistors;

a fifth transistor coupled to a node at the first supply voltage;

a sixth transistor coupled to the fifth transistor;

a seventh transistor coupled to a node at the second supply voltage; and

an eighth transistor coupled to the seventh transistor wherein the eighth transistor is directly coupled to each of the fifth and the sixth transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, and wherein the second input signal is inverted relative to the first input signal.

12. The level shifter circuit of claim 11 further comprising:

a ninth transistor coupled between the second transistor and a node at a ground voltage, wherein the ninth transistor receives the first input signal at a fifth control input; and

a tenth transistor coupled between the sixth transistor and a node at the ground voltage, wherein the tenth transistor receives the second input signal at a sixth control input, and the second supply voltage is less than the first supply voltage.

13. A level shifter circuit comprising:

a first transistor coupled to a node at a first supply voltage;

a second transistor coupled to the first transistor;

a third transistor coupled to a node at a second supply voltage;

a fourth transistor coupled to the first, the second, and the third transistors;

a fifth transistor coupled to a node at the first supply voltage;

a sixth transistor coupled to the fifth transistor;

a seventh transistor coupled to a node at the second supply voltage; and

an eighth transistor coupled to the fifth, the sixth, and the seventh transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, wherein the third transistor receives the first input signal at a fifth control input, and wherein the seventh transistor receives the second input signal at a sixth control input.

14. The level shifter circuit of claim 13, wherein the first and the fifth transistors are cross-coupled, and wherein the level shifter circuit generates a level shifted output signal at a node between the first and the second transistors in response to the first and the second input signals.

15. The level shifter circuit of claim 14, wherein the fourth transistor is directly coupled to each of the first, the second, and the third transistors, and wherein the eighth transistor is directly coupled to each of the fifth, the sixth, and the seventh transistors.

16. A level shifter circuit comprising:

a first transistor coupled to a node at a first supply voltage;

a second transistor coupled to the first transistor;

a third transistor coupled to a node at a second supply voltage;

a fourth transistor coupled to the first, the second, and the third transistors;

a fifth transistor coupled to a node at the first supply voltage;

a sixth transistor coupled to the fifth transistor;

a seventh transistor coupled to a node at the second supply voltage; and

an eighth transistor coupled to the fifth, the sixth, and the seventh transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, and wherein each of the third, the seventh, the ninth, and the tenth transistors has a thinner oxide thickness than each of the first, the second, the fourth, the fifth, the sixth, and the eighth transistors.

17. A method comprising:

pulling an output signal to a low voltage through a first current path in response to a first input signal;

pulling a voltage at a node to a first supply voltage through a second current path in response to the first input signal and a second inverted input signal;

pulling the voltage at the node to a second supply voltage through a third current path in response to the output signal;

pulling the voltage at the node to the low voltage through a fourth current path in response to the second inverted input signal;

pulling the output signal to the first supply voltage through a fifth current path in response to the first input signal and the second inverted input signal; and

pulling the output signal to the second supply voltage through a sixth current path in response to the voltage at the node in order to level shift the output signal.

18. The method of claim 17 further comprising:

turning off the second current path in response to the first input signal and the second inverted input signal; and

turning off the fifth current path in response to the first input signal and the second inverted input signal.

19. The method of claim 17 further comprising:

turning off the third current path in response to the output signal; and

turning off the sixth current path in response to the voltage at the node.

20. The method of claim 17 further comprising:

turning off the first current path in response to the first input signal; and

turning off the fourth current path in response to the second inverted input signal.