Level shifter circuits and methods
First Claim
1. A level shifter circuit comprising:
- first and second transistors, wherein the first transistor is directly coupled to the second transistor at a first node;
third and fourth transistors coupled in series, wherein the fourth transistor is coupled to the first node;
fifth and sixth transistors, wherein the fifth transistor is directly coupled to the sixth transistor at a second node; and
seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to the second node, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, and wherein the second input signal is inverted relative to the first input signal.
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Abstract
A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.
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Citations
20 Claims
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1. A level shifter circuit comprising:
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first and second transistors, wherein the first transistor is directly coupled to the second transistor at a first node; third and fourth transistors coupled in series, wherein the fourth transistor is coupled to the first node; fifth and sixth transistors, wherein the fifth transistor is directly coupled to the sixth transistor at a second node; and seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to the second node, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, and wherein the second input signal is inverted relative to the first input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A level shifter circuit comprising:
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first and second transistors coupled in series; third and fourth transistors coupled in series, wherein the fourth transistor is coupled to a first node between the first and the second transistors; fifth and sixth transistors coupled in series; and seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to a second node between the fifth and the sixth transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, wherein the third transistor receives the first input signal at a fifth control input, and wherein the seventh transistor receives the second input signal at a sixth control input. - View Dependent Claims (9)
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10. A level shifter circuit comprising:
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first and second transistors coupled in series; third and fourth transistors coupled in series, wherein the fourth transistor is coupled to a first node between the first and the second transistors; fifth and sixth transistors coupled in series; and seventh and eighth transistors coupled in series, wherein the eighth transistor is coupled to a second node between the fifth and the sixth transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, and wherein each of the third, the seventh, the ninth, and the tenth transistors has a thinner oxide thickness than each of the first, the second, the fourth, the fifth, the sixth, and the eighth transistors.
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11. A level shifter circuit comprising:
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a first transistor coupled to a node at a first supply voltage; a second transistor coupled to the first transistor; a third transistor coupled to a node at a second supply voltage; a fourth transistor coupled to the third transistor, wherein the fourth transistor is directly coupled to each of the first and the second transistors; a fifth transistor coupled to a node at the first supply voltage; a sixth transistor coupled to the fifth transistor; a seventh transistor coupled to a node at the second supply voltage; and an eighth transistor coupled to the seventh transistor wherein the eighth transistor is directly coupled to each of the fifth and the sixth transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, and wherein the second input signal is inverted relative to the first input signal. - View Dependent Claims (12)
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13. A level shifter circuit comprising:
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a first transistor coupled to a node at a first supply voltage; a second transistor coupled to the first transistor; a third transistor coupled to a node at a second supply voltage; a fourth transistor coupled to the first, the second, and the third transistors; a fifth transistor coupled to a node at the first supply voltage; a sixth transistor coupled to the fifth transistor; a seventh transistor coupled to a node at the second supply voltage; and an eighth transistor coupled to the fifth, the sixth, and the seventh transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, wherein the third transistor receives the first input signal at a fifth control input, and wherein the seventh transistor receives the second input signal at a sixth control input. - View Dependent Claims (14, 15)
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16. A level shifter circuit comprising:
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a first transistor coupled to a node at a first supply voltage; a second transistor coupled to the first transistor; a third transistor coupled to a node at a second supply voltage; a fourth transistor coupled to the first, the second, and the third transistors; a fifth transistor coupled to a node at the first supply voltage; a sixth transistor coupled to the fifth transistor; a seventh transistor coupled to a node at the second supply voltage; and an eighth transistor coupled to the fifth, the sixth, and the seventh transistors, wherein the second transistor receives a first input signal at a first control input, wherein the eighth transistor receives the first input signal at a second control input, wherein the fourth transistor receives a second input signal at a third control input, wherein the sixth transistor receives the second input signal at a fourth control input, wherein the second input signal is inverted relative to the first input signal, and wherein each of the third, the seventh, the ninth, and the tenth transistors has a thinner oxide thickness than each of the first, the second, the fourth, the fifth, the sixth, and the eighth transistors.
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17. A method comprising:
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pulling an output signal to a low voltage through a first current path in response to a first input signal; pulling a voltage at a node to a first supply voltage through a second current path in response to the first input signal and a second inverted input signal; pulling the voltage at the node to a second supply voltage through a third current path in response to the output signal; pulling the voltage at the node to the low voltage through a fourth current path in response to the second inverted input signal; pulling the output signal to the first supply voltage through a fifth current path in response to the first input signal and the second inverted input signal; and pulling the output signal to the second supply voltage through a sixth current path in response to the voltage at the node in order to level shift the output signal. - View Dependent Claims (18, 19, 20)
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Specification