Method and apparatus for generating a target frequency having an over-sampled data rate using a system clock having a different frequency

• US 7,994,947 B1
• Filed: 06/05/2009
• Issued: 08/09/2011
• Est. Priority Date: 06/06/2008
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Ledzius, Robert Charles
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US12/479,529
• Time in Patent Office: 795 Days
• Field of Search: 341/61, 341/50, 341/51
• US Class Current: 341/61
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Method and apparatus for generating a target frequency having an over-sampled data rate using a system clock having a different frequency are disclosed. In one aspect of the present disclosure, the circuit includes, a digital phase locked loop coupled to the system clock. The digital phase locked loop including an oscillator output and an oscillator input. The circuit further comprises an extra pulse eliminator coupled to the oscillator output. The extra pulse eliminator includes an extra pulse eliminator output. One or more frequency dividers may be coupled to an extra pulse eliminator output.

Claims

1. A circuit for generating a target frequency having an over-sampled data rate using a system clock having a different frequency, the circuit, comprising:

a digital phase locked loop coupled to the system clock, the digital phase locked loop having an oscillator output and an oscillator input, wherein the digital phase locked loop comprises a digital numerical controlled oscillator comprising,

a multi-bit integrator having a multi-bit numerical input and a single bit overflow output, when, in operation, the multi-bit integrator is clocked by the system clock, wherein, the multi-bit integrator comprises;

a multi-bit full adder having an adder output and the multi-bit numerical input; and

a multi-bit register coupled to the adder output;

an extra pulse eliminator coupled to the oscillator output, the extra pulse eliminator having an extra pulse eliminator output; and

one or more frequency dividers coupled to an extra pulse eliminator output.

2. The circuit of claim 1, wherein

the multi-bit register comprises a plurality of flip-flops.

3. A circuit for generating a target frequency having an over-sampled data rate using a system clock having a different frequency, the circuit, comprising:

a digital phase locked loop coupled to the system clock, the digital phase locked loop comprising a digital numerical controlled oscillator having an oscillator output and an oscillator input;

an extra pulse eliminator coupled to the oscillator output, the extra pulse eliminator having an extra pulse eliminator output;

one or more frequency dividers coupled to an extra pulse eliminator output; and

an N-calculator coupled to the oscillator input,

wherein the N-calculator comprises;

a one-shot edge detector comprising a detector output;

a frequency counter coupled to the detector output, the frequency counter comprising a counter output;

an error calculator coupled to the counter output, the error calculator comprising a calculator output; and

a frequency index calculator coupled to the counter output, the frequency index calculator comprising a calculator output coupled to an input of the digital numerical controlled oscillator.

4. The circuit of claim 3, wherein, the one-shot edge detector comprises:

a latch having an edge triggered latch output and a reset node;

a shift-register comprising at least a first flip-flop coupled in series with a second flip-flop, the second flip-flop having an input node and an output node; and

a logic gate having a first input coupled to the input node of the second flip-flop and a second input coupled to the output node of the second flip-flop to detect a rising edge, and the logic gate output coupled to the reset node of the latch.

5. The circuit of claim 4, wherein, the logic gate comprises an AND gate;

wherein the second input of the AND gate is inverted.

6. The circuit of claim 4, further comprising, another flip-flop coupled in series between the latch and the first flip-flop, wherein the another flip-flop is coupled to the latch output.

7. The circuit of claim 4, wherein, the first flip-flop is coupled to the latch output.

8. A method for generating an internal clock signal from a system clock, comprising:

identifying a frequency of a left-right clock;

determining a driver signal based on a target frequency of the internal clock signal and an over-sampled data rate determined according to the frequency of the left-right clock;

applying the driver signal to a phase detector of a digital numerical controlled oscillator, the digital numerical controlled oscillator comprises an output; and

retrieving a most significant overflow bit of the output to generate the internal clock signal.

9. The method of claim 8, further comprising, frequency dividing the internal clock frequency to generate one or more additional clock frequencies.

10. The method of claim 8, further comprising,

generating the driver signal in a slave mode of operation, wherein, the generating comprises:

detecting a rising edge of the left-right clock;

generating a frequency differential value by comparing a frequency of the internal clock signal with the target frequency; and

adjusting the driver signal based on the frequency differential value.

11. The method of claim 8, wherein, the driver signal is predetermined.

12. The method of claim 8, wherein, the system clock is substantially within a range of 5 MHz and 25 MHz.

13. The method of claim 12, wherein, the target frequency of the internal clock signal is substantially between 6 kHz to 52 kHz.

14. The method of claim 8, further comprising, operating in a master mode of operation via determining the driver signal based on user input.

15. The method of claim 8, wherein the left-right clock signal is digitally jittered.