Arbitration for acquisition of extended display identification data (EDID)

• US 7,995,043 B2
• Filed: 02/18/2005
• Issued: 08/09/2011
• Est. Priority Date: 10/18/2004
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Inventors: Noorbakhsh, Ali, Lattanzi, John, Keene, David, Chilukuri, Ram
• Primary Examiner(s): Nguyen; Chanh
• Assistant Examiner(s): Mistry; Ram A
• Application Number:
  US11/060,873
• Publication Number:
  US 20060082586A1
• Time in Patent Office: 2,363 Days
• Field of Search: 345/535, 345/699, 345/581, 345/100, 345/530, 345/558, 345211-213, 345/204, 713/300, 713/320, 713/340, 713/52, 710/29, 710 53- 57
• US Class Current: 345/204
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A display controller includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller, a data buffer for storing EDID read from the memory device, and an arbitration circuit for arbitrating memory device access requests between the processor and a requesting data port wherein when the data buffer is not almost empty, then the arbitration circuit grants the processor access to the memory wherein when the data buffer is almost empty, then the arbitration circuit grants only the requesting data port access to them memory so as to replenish the data buffer with read EDID.

Claims

1. A method, executed by an Extended Display Information Data compliant display controller, for providing power to a memory device to access Extended Display Information Data stored in the memory device, the method comprising:

providing power from an external power supply via a data port to the memory device to access the Extended Display Information Data while an on-board controller power supply is turned off;

detecting that the on-board controller power supply is switched from off to on;

determining whether a memory device access request for Extended Display Information Data from a data port has been completed;

in response to detecting that the on-board controller power supply is switched from off to on and determining that the memory device access request has not been completed, completing the memory device access request for Extended Display Information Data by continuing to provide the power from the external power supply to the memory device; and

in response to determining that the memory device access request for Extended Display Information Data has been completed or that no memory device access request for Extended Display Information Data from a data port has been detected, switching from providing power to the memory device from the external power supply to providing power to the memory device from the on-board controller power supply to access the Extended Display Information Data; and

arbitrating memory device access requests between data ports and client devices.

2. The method as recited in claim 1, wherein arbitrating memory device access requests between data ports and client devices comprises:

receiving a memory device access request from a data port, the memory device access request including a request for Extended Display Information Data;

accessing a single memory device to read the Extended Display Information Data;

storing the Extended Display Information Data read from the accessed single memory device to a data buffer, the Extended Display Information Data being read and stored in data increments;

sending the stored Extended Display Information Data to the data port;

interrupting processing of a memory device access request to the single memory device from a client device in response to detecting that a volume of the Extended Display Information Data in data increments in the data buffer has fallen below a predetermined level; and

continuing the processing of the memory device access request from a client device in response to detecting that the data buffer has stored the Extended Display Information Data in data increments to a data buffer capacity or detecting that the request for Extended Display Information Data has been fulfilled.

3. The method as recited in claim 2, wherein the data buffer is a first in first out (FIFO) data buffer.

4. The method as recited in claim 2, wherein the requesting port is granted access to the single memory device by the arbitration circuit.

5. The method as recited in claim 4, further comprising:

setting a hold flag in response to detecting that the volume of the Extended Display Information Data in data increments in the data buffer has fallen below a predetermined level; and

releasing the hold flag in response to determining that the data buffer is full, wherein the hold flag indicates that the processing of the single memory device access request from a client device must be interrupted.

6. The method as recited in claim 1, further comprising turning off a low frequency clock and activating an on-board crystal clock.

7. The method as recited in claim 6, wherein detecting that the on-board controller power supply is switched from off to on includes detecting activity of the on-board crystal clock.

8. A display controller coupled to a display device by way of a display interface and to a host device by way of one or more data ports, the display controller comprising:

a processor configured to process executable instructions and associated data;

an on-board controller power supply;

a circuit configured to;

provide power from an external power supply via a data port of the one or more data ports to a memory device;

detect that the on-board controller power supply is switched from off to on;

determine whether a memory device access request for Extended Display Information Data from a data port has been completed;

delay providing power from the on-board controller power supply to the memory device in response to determining that the memory device access request has not been completed and detecting the on-board controller power supply has been switched from off to on; and

direct the controller to switch from providing power to the memory device from the external power supply to providing power to the memory device from the on-board controller power supply in response to determining that the memory device access request for Extended Display Information Data has been completed or determining that no memory device access request for Extended Display Information Data has been detected; and

a memory device for storing executable instructions, associated data, and Extended Display Information Data corresponding to the display device, the memory device being available for access by the data ports regardless of a power state of the display controller.

9. The display controller as recited in claim 8, further comprising:

a data buffer for storing Extended Display Information Data read from the memory device; and

an arbitration circuit for arbitrating memory device access requests between a client device and a data port, the arbitration circuit being associated with a processor;

wherein the arbitration circuit is configured to direct the processor to interrupt processing of a memory device access request to the memory device from a client device in response to detecting that a volume of the Extended Display Information Data in the data buffer has fallen below a predetermined level, and wherein the arbitration circuit is configured to direct the processor to continue the processing of the single memory device access request from the client device in response to detecting that the data buffer has stored the Extended Display Information Data in data increments to a data buffer capacity or detecting that the request for Extended Display Information Data has been fulfilled.

10. The display controller as recited in claim 9, further comprising:

a bridge portion coupling the data ports and the memory device, wherein the bridge portion and the memory device are both provided power from the external power supply such that the host device retrieves the appropriate Extended Display Information Data from the memory device as needed while the on-board controller power supply is in an off state.

11. The display controller as recited in claim 10, wherein the memory device is a non-volatile random access memory device.

12. The display controller as recited in claim 11, wherein the display controller is a dual port controller configured to control an analog type display and a digital type display.

13. The display controller as recited in claim 9, wherein a portion of the memory device allocated for storage of the Extended Display Information Data is further partitioned into an analog Extended Display Information Data portion and a digital Extended Display Information Data portion.

14. The display controller as recited in claim 13, further comprising:

a display type determinator arranged to determine if the display is an analog or digital display; and

a port activator coupled to the display type determinator and configured to activate an appropriate port based on the results of the determination of the display type.

15. The display controller as recited in claim 9, wherein the data buffer is a first in first out (FIFO) data buffer.

16. The display controller as recited in claim 8, further comprising an auto activity detection circuit configured to charge a capacitor in response to detecting toggling of a reference clock signal.

17. The display controller as recited in claim 16, wherein the capacitor is configured to cause a logic state change indicating that the on-board controller power supply is switched from off to on in response to a voltage of the capacitor exceeding a threshold voltage.

18. The display controller as recited in claim 17, wherein the circuit is configured to detect that the on-board controller power supply is switched from off to on by detecting the logic state change and by detecting the reference clock signal.

19. A VESA-compliant computer display, comprising:

a single memory device configured to store executable instructions, associated data, and Extended Display Information Data;

a processor configured to facilitate an access to the single memory device, wherein the processor and the single memory circuit are coupled by an I2C-compliant data bus; and

one or more ports configured to allow a computer to supply power to the single memory device and read the Extended Display Information Data stored in the single memory device according to a VESA protocol in response to the processor accepting a single memory device access request from the computer,

wherein the computer display is configured to, if an on-board computer display power supply is switched from off to on during the reading of the Extended Display Information Data by the computer, delay switching from supplying power to the single memory device from the one or more ports to supplying power to the single memory device from the on-board computer display power supply until the computer completes the reading of the Extended Display Information Data.

20. The display of claim 19, further comprising:

a data buffer configured to access the single memory device and to store the Extended Display Information Data requested by a port, wherein the processor is programmed to interrupt memory device access requests to the single memory device from a client device associated with the processor in response to detecting that a volume of the Extended Display Information Data stored in the data buffer has fallen below a predetermined level and to resume processing the memory device access request from the client device in response to detecting that the data buffer is full.