MRAM device with shared source line

• US 7,995,378 B2
• Filed: 12/19/2007
• Issued: 08/09/2011
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Abu-Rahma, Mohamed H., Zhong, Cheng, Yoon, Sei Seung, Park, Dongkyu
• Primary Examiner(s): Elms; Richard
• Assistant Examiner(s): Byrne; Harry W
• Application Number:
  US11/959,515
• Publication Number:
  US 20090161413A1
• Time in Patent Office: 1,329 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/225.5, 365/243.5, 216/22, 257/3, 257/421, 257/E21.665, 438/3, 977933-935
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell.

Claims

1. A memory device comprising:

a first memory element having a first memory element first terminal and a first memory element second terminal;

a second memory element having a second memory element first terminal and a second memory element second terminal;

a first bit line coupled to the first memory element at the first memory element first terminal, the first bit line biased to a first voltage;

a second bit line coupled to the second memory element at the second memory element first terminal, the second bit line biased to a second voltage that is independent of the first voltage; and

a source line, the source line biased to the second voltage;

wherein upon activation of a first switch the source line is coupled to the first memory element at the first memory element second terminal and wherein upon activation of a second switch the source line is coupled to the second memory element at the second memory element second terminal.

2. The memory device of claim 1, wherein each of the first memory element and the second memory element includes a respective magnetic tunnel junction (MTJ) device.

3. The memory device of claim 1, further comprising a word line coupled to the first switch and to the second switch, wherein upon application of a predefined voltage to the word line, the first switch is activated and the second switch is activated.

4. The memory device of claim 1, wherein, during a read of the first memory element, the first switch is activated and the second switch is activated.

5. The memory device of claim 1, further comprising:

a first word line configured to selectively activate the first memory element but not the second memory element; and

a second word line configured to selectively activate the second memory element but not the first memory element.

6. The memory device of claim 1, wherein data stored in the first memory element is read by:

activation of the first switch and the second switch via a control signal sent via a word line;

and

upon activation of the first switch and the second switch, comparison of a current flowing through the source line to a reference current.

7. The memory device of claim 1, wherein data is stored in the first memory element by:

activation of the first switch via a control signal sent via a word line; and

application of an electrical current to the source line after the activation of the first switch, wherein a magnitude of the electrical current exceeds a threshold magnitude associated with a change in direction of a programmable magnetic field of a magnetic tunnel junction (MTJ) device associated with the first memory element.

8. The memory device of claim 1, wherein the first voltage differs from the second voltage during a read operation of the first memory element.

9. The memory device of claim 1, wherein the first voltage differs from the second voltage during a write operation to the first memory element.

10. A memory device comprising:

a first memory element, wherein the first memory element is coupled to a first bit line and the first memory element is coupleable to a source line;

a second memory element, wherein the second memory element is coupled to a second bit line and the second memory element is coupleable to the source line; and

circuitry to perform a read operation with respect to the first memory element by;

coupling the source line to the first memory element and to the second memory element;

providing a first voltage to the first bit line;

providing a second voltage to the second bit line, wherein the second voltage differs from the first voltage; and

providing the second voltage to the source line.

11. The memory device of claim 10, wherein the first memory element comprises:

a first memory element first terminal, wherein the first memory element is coupled to the first bit line via the first memory element first terminal; and

a first memory element second terminal, wherein the first memory element is coupleable to the source line via the first memory element second terminal.

12. The memory device of claim 10, wherein the second memory element comprises:

a second memory element first terminal, wherein the second memory element is coupled to the second bit line via the second memory element first terminal; and

a second memory element second terminal, wherein the second memory element is coupleable to the source line via the second memory element second terminal.

13. The memory device of claim 10, wherein the circuitry is operable to couple the source line to the first memory element by actuating a first switch and wherein the circuitry is operable to couple the source line to the second memory element by actuating a second switch.

14. The memory device of claim 10, wherein the first memory element comprises a first magnetic tunnel junction (MTJ) device and wherein the second memory element comprises a second MTJ device.