System and method to read data subject to a disturb condition

• US 7,995,387 B2
• Filed: 01/30/2009
• Issued: 08/09/2011
• Est. Priority Date: 01/30/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Alrod, Idan, Sharon, Eran
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US12/363,554
• Publication Number:
  US 20100195384A1
• Time in Patent Office: 921 Days
• Field of Search: 365/185.02, 365/185.03
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Systems and methods for reading data are disclosed. In a particular embodiment, a method includes measuring characteristics of a plurality of cells at a memory. The characteristics correspond to a plurality of values including a first value stored at a particular cell and a second value stored at a second cell of the memory. The method includes testing whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the particular cell, and providing a data value corresponding to the particular cell. The data value is determined at least in part based on a result of the testing.

Claims

1. A method of determining a data value stored at a particular cell of a memory, the method comprising:

measuring characteristics of a plurality of cells at the memory, the characteristics corresponding to a plurality of values including a first value stored at the particular cell and a second value stored at a second cell of the memory;

testing whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the particular cell; and

providing a data value corresponding to the particular cell, wherein the data value is determined at least in part based on a result of the testing.

2. The method of claim 1, wherein the disturb condition is a read disturb condition.

3. The method of claim 1, wherein the disturb condition is a program disturb condition.

4. The method of claim 1, wherein the memory is a flash memory.

5. The method of claim 1, wherein the particular cell is coupled to a particular bit line and to a particular word line, and wherein the second cell is coupled to the particular bit line and to a second word line.

6. The method of claim 5, wherein the plurality of values includes a third value stored at a third cell of the memory, wherein the third cell is coupled to the particular bit line and to a third word line, and wherein the particular word line is located between the second word line and the third word line.

7. The method of claim 1, wherein the testing identifies a risk of the first value having the disturb condition without determining cross-coupling coefficients.

8. The method of claim 1, wherein the disturb condition indicates that a probability of an error in the first value due to a data write operation occurring at the second cell is greater than a predetermined probability.

9. The method of claim 1, wherein the particular pattern is empirically determined to indicate the disturb condition.

10. The method of claim 1, wherein the testing whether at least some of the plurality of values match the particular pattern includes determining whether at least one value of the plurality of values exceeds a first predetermined amount.

11. The method of claim 1, wherein the testing whether at least some of the plurality of values match the particular pattern includes determining whether at least one value of the plurality of values does not exceed a second predetermined amount.

12. The method of claim 1, wherein the testing comprises:

comparing the plurality of values to a plurality of predetermined patterns to locate a matching pattern, wherein at least a first predetermined pattern of the plurality of predetermined patterns corresponds to a first classification that indicates the disturb condition, and wherein at least a second predetermined pattern of the plurality of predetermined patterns corresponds to a second classification not indicating the disturb condition; and

classifying the plurality of values as having one of the first classification and the second classification based on the matching pattern.

13. The method of claim 12, wherein the first predetermined pattern corresponds to a probability of a disturb error that is greater than a first threshold, wherein the second predetermined pattern corresponds to a probability of a disturb error that is less than a second threshold, and wherein a third predetermined pattern of the plurality of predetermined patterns corresponds to a probability of a disturb error that is not greater than the first threshold and not less than the second threshold.

14. The method of claim 1, wherein the providing a data value comprises:

selecting a reliability measure associated with the particular pattern;

providing the first value and the reliability measure to an error correction code (ECC) decoder; and

activating the ECC decoder to determine the data value based on the first value and the reliability measure.

15. A method of reading data, comprising:

reading a first cell to obtain a first measurement of a first value of a physical property of the first cell of a memory, the first value corresponding to first data stored at the first cell;

reading a second cell to obtain a second measurement of a second value of a physical property of the second cell of the memory, the second value corresponding to second data stored at the second cell; and

generating an estimation of particular data stored at a particular cell based at least partially on the first measurement and the second measurement, wherein generating the estimation includes classifying a combination of at least the first measurement and the second measurement into a particular class of a group of at least two classes, wherein at least one class of the group of at least two classes is a class of combination measurement values that are determined to correlate to the particular cell being prone to a disturb error.

16. The method of claim 15, wherein the disturb error includes a programming-time disturb error.

17. The method of claim 15, wherein the disturb error includes a read-time disturb error.

18. The method of claim 15, wherein the particular cell is the first cell.

19. The method of claim 15, wherein the first cell and the second cell are neighbor cells to the particular cell.

20. The method of claim 19, wherein at least one of the neighbor cells is coupled to a same bit line as the particular cell, and wherein the at least one of the neighbor cells is coupled to a different word line than the particular cell.

21. The method of claim 19, further comprising reading the particular cell to obtain a third measurement of a third value of a physical property of the particular cell, and wherein the combination further includes the third measurement.

22. The method of claim 15, wherein the second cell is at a location within the memory relative to the particular cell such that a data write to the second cell can potentially disturb a value of a physical property of the particular cell.

23. The method of claim 15, wherein the first cell and the second cell are flash cells, and wherein the physical property of the first cell is a threshold voltage of the first cell, and wherein the physical property of the second cell is a threshold voltage of the second cell.

24. The method of claim 23, wherein the classifying a combination of at least the first measurement and the second measurement comprises:

generating a first binary value indicating whether the first measurement satisfies a first condition and a second binary value indicating whether the second measurement satisfies a second condition; and

performing a logical operation on the first binary value and the second binary value to determine the particular class.

25. The method of claim 23, wherein the classifying a combination of at least the first measurement and the second measurement comprises:

generating a vector including a first binary value that indicates whether the first measurement satisfies a first condition and a second binary value that indicates whether the second measurement satisfies a second condition, wherein each of four possible values of the vector represents a corresponding class of four distinct classes, and wherein each distinct class is associated with a corresponding reliability measure;

determining a particular reliability measure of the particular data based on the corresponding class represented by the vector; and

providing the particular reliability measure to an error correction code (ECC) decoder.

26. In a flash device that includes an array of memory cells and a circuit to read states of multiple memory cells and to compare the read states to at least two reference voltage levels defining at least three memory state ranges, a method comprising:

reading memory states of a plurality of cells adjacent to an addressed set of cells, wherein a memory state of each cell of the addressed set of cells is associated with at least one corresponding cell of the plurality of cells; and

for each particular cell of the addressed set of cells;

classifying joint states of cells associated with the particular cell into a particular class of a group of at least two classes based on matching the joint states to a particular pattern of values that is determined to correspond to one of the at least two classes; and

providing a data value of the particular cell in accordance with the particular class.

27. The method of claim 26, wherein at least one class of the group of at least two classes indicates a correlation between the joint states of the cells associated with the particular cell and the particular cell being prone to a programming disturb.

28. The method of claim 26, wherein at least one class of the group of at least two classes indicates a correlation between the joint states of the cells associated with the particular cell and the particular cell being prone to a read disturb.

29. In a flash device that includes an array of memory cells and a circuit to read states of multiple memory cells in the array of memory cells and to compare the read states to at least two reference voltage levels defining at least three memory state ranges, a method comprising:

reading memory states of a plurality of cells adjacent to an addressed set of cells, wherein a memory state of each cell of the addressed set of cells is associated with at least one cell of the plurality of cells; and

for each particular cell of the addressed set of cells;

classifying joint states of cells associated with the particular cell into a particular class of a group of at least two classes, wherein a first class of the group of at least two classes indicates a determined correlation indicating that the particular cell is prone to a disturb condition; and

adjusting a reliability measure of data stored in the particular cell in accordance with the particular class.

30. The method of claim 29, wherein the disturb condition is a program disturb condition.

31. The method of claim 29, wherein the disturb condition is a read disturb condition.

32. The method of claim 29, wherein the determined correlation is empirically determined.

33. The method of claim 29, wherein the classifying comprises generating a vector having a binary value for each particular cell of the addressed set of cells, wherein the binary value indicates whether the joint states of the cells associated with the corresponding particular cell are classified under the first class.

34. The method of claim 29, wherein the classifying comprises generating a vector having a classification indicator for each particular cell of the addressed set of cells, wherein the classification indicator indicates a class of the corresponding particular cell based on the joint states of the cells associated with the corresponding particular cell.

35. The method of claim 29, further comprising providing the reliability measure to an error correction code (ECC) decoder.

36. The method of claim 29, wherein the plurality of cells includes at least two cells sharing a bit line with a corresponding cell of the addressed set of cells.

37. A memory device comprising:

an array of memory cells;

a read circuit coupled to the array of memory cells, wherein the read circuit is configured to read a state of an addressed memory cell and to compare the state to at least one reference voltage level associated with at least two memory state ranges; and

a controller coupled to the read circuit, wherein the controller is configured to initiate a read operation to read a first value stored at a first memory cell and to read a second value stored at a second memory cell, wherein the controller is further configured to compare at least the first value and the second value to a predetermined pattern, wherein the predetermined pattern corresponds to a potential probability of a disturb error with respect to a value stored at the addressed memory cell.

38. The memory device of claim 37, wherein the first memory cell is the addressed memory cell.

39. The memory device of claim 37, wherein the first memory cell and the second memory cell are neighbor cells to the addressed memory cell.

40. The memory device of claim 37, wherein the disturb error includes a program disturb error.

41. The memory device of claim 37, wherein the disturb error includes a read disturb error.

42. The memory device of claim 37, wherein the predetermined pattern includes a first threshold and wherein the second value exceeds the first threshold.

43. The memory device of claim 37, wherein the predetermined pattern includes a second threshold and wherein the second value does not exceed the second threshold.

44. The memory device of claim 37, further comprising an error correction code (ECC) decoder coupled to the controller, and wherein the controller is configured to provide a reliability measure to the ECC decoder based on whether the first value and the second value match the predetermined pattern.

45. A data storage device comprising:

a memory including a plurality of memory elements;

a read circuit coupled to the memory, wherein the read circuit is configured to read a state of an addressed memory element of the plurality of memory elements and to compare the state to at least one reference voltage level associated with at least two memory state ranges; and

a controller coupled to the read circuit, wherein the controller is configured to initiate a read operation to read a first value stored at a first memory element of the plurality of memory elements and to read a second value stored at a second memory element of the plurality of memory elements, wherein the controller is further configured to compare at least the first value and the second value to a pattern, wherein the pattern corresponds to a probability of a disturb error with respect to a value stored at the addressed memory element.

46. The data storage device of claim 45, wherein the first memory element is the addressed memory element.

47. The data storage device of claim 45, wherein the first memory element and the second memory element are neighbor elements to the addressed memory element.

48. The data storage device of claim 45, wherein the disturb error includes a program disturb error.

49. The data storage device of claim 45, wherein the disturb error includes a read disturb error.

50. The data storage device of claim 45, further comprising an error correction code (ECC) decoder coupled to the controller, and wherein the controller is configured to provide a reliability measure to the ECC decoder based on whether the first value and the second value match the pattern.