Data storage using modified voltages

• US 7,995,388 B1
• Filed: 08/04/2009
• Issued: 08/09/2011
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Winter, Shai
• Primary Examiner(s): Ho; Hoai V
• Application Number:
  US12/534,898
• Time in Patent Office: 735 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.17, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing an input storage value into the target memory cell. A first read operation, which reads a first output storage value from the target memory cell while biasing the other memory cells with respective first pass voltages, is applied to the target memory cell. A second read operation, which reads a second output storage value from the target memory cell while biasing the other memory cells with respective second pass voltages, is applied to the target memory cell. At least one of the second pass voltages is different from a respective first pass voltage. The data is reconstructed responsively to the first and second output storage values.

Claims

1. A method for data storage, comprising:

storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing an input storage value into the target memory cell;

applying to the target memory cell a first read operation, which reads a first output storage value from the target memory cell while biasing the other memory cells in the group with respective first pass voltages;

applying to the target memory cell a second read operation, which reads a second output storage value from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is different from a respective first pass voltage applied to the one of the other memory cells;

making an assessment of whether the second output storage value has been distorted due to the at least one of the second pass voltages; and

reconstructing the data responsively to the assessment and to the first and second output storage values.

2. The method according to claim 1, wherein the analog memory cells comprise NAND Flash memory cells, and wherein the group of the analog memory cells comprises a NAND string.

3. The method according to claim 1, wherein applying the second read operation comprises applying the different at least one of the second pass voltages to a memory cell that neighbors the target memory cell.

4. The method according to claim 1, wherein making the assessment comprises reading third output storage values from one or more of the other memory cells in the group, and assessing whether the second output storage value has been distorted based on the third output storage values.

5. The method according to claim 1, wherein applying the second read operation comprises reading the target memory cell using a first read voltage, and wherein making the assessment comprises reading a third storage value from the target memory cell using a second read voltage, higher than the first read voltage, while biasing the other memory cells in the group with the respective second pass voltages, and assessing whether the second output storage value has been distorted based on the third output storage value.

6. The method according to claim 1, wherein recovering the data comprises assigning the target memory cell a confidence level based on the assessment and the first and second output storage values, and decoding the data based on the confidence level.

7. The method according to claim 6, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and wherein decoding the data comprises decoding the ECC based on the confidence level.

8. The method according to claim 1, and comprising iteratively modifying the at least one of the second pass voltages applied during the second read operation, and repeating the assessment with respect to the modified at least one of the second pass voltages.

9. The method according to claim 1, and comprising applying the second read operation and making the assessment only responsively to a failure to reconstruct the data based on the first read operation.

10. The method according to claim 1, wherein the memory cells are comprised in a memory device, and wherein applying the second read operation comprises instructing the memory device, using a processor separate from the memory device, to apply the at least one of the second pass voltages.

11. Apparatus for data storage, comprising:

an interface, which is operative to communicate with a memory comprising a group of analog memory cells that are connected in series with one another; and

circuitry, which is configured to store data in a target analog memory cell in the group by writing an input storage value into the target memory cell, to apply to the target memory cell a first read operation, which reads a first output storage value from the target memory cell while biasing the other memory cells in the group with respective first pass voltages, to apply to the target memory cell a second read operation, which reads a second output storage value from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is different from a respective first pass voltage applied to the one of the other memory cells, to make an assessment of whether the second output storage value has been distorted due to the at least one of the second pass voltages, and to reconstruct the data responsively to the assessment and to the first and second output storage values.

12. The apparatus according to claim 11, wherein the analog memory cells comprise NAND Flash memory cells, and wherein the group of the analog memory cells comprises a NAND string.

13. The apparatus according to claim 11, wherein the circuitry is configured to apply the different at least one of the second pass voltages to a memory cell that neighbors the target memory cell.

14. The apparatus according to claim 11, wherein the circuitry is configured to read third output storage values from one or more of the other memory cells in the group, and to assess whether the second output storage value has been distorted based on the third output storage values.

15. The apparatus according to claim 11, wherein the circuitry is configured to read the target memory cell in the second read operation using a first read voltage, to read a third storage value from the target memory cell using a second read voltage, higher than the first read voltage, while biasing the other memory cells in the group with the respective second pass voltages, and to assess whether the second output storage value has been distorted based on the third output storage value.

16. The apparatus according to claim 11, wherein the circuitry is configured to assign the target memory cell a confidence level based on the assessment and the first and second output storage values, and to decode the data based on the confidence level.

17. The apparatus according to claim 16, wherein the circuitry is configured to encode the stored data with an Error Correction Code (ECC), and to decode the ECC based on the confidence level.

18. The apparatus according to claim 11, wherein the circuitry is configured to iteratively modify the at least one of the second pass voltages applied during the second read operation, and to repeat the assessment with respect to the modified at least one of the second pass voltages.

19. The apparatus according to claim 11, wherein the circuitry is configured to apply the second read operation and make the assessment only responsively to a failure to reconstruct the data based on the first read operation.

20. The apparatus according to claim 11, wherein the circuitry comprises:

a Read/Write unit, which is comprised in a memory device comprising the memory cells; and

a processor, which is separate from the memory device and is configured to instruct the R/W unit to apply the at least one of the second pass voltages.