Semiconductor memory device capable of shortening erase time
First Claim
1. A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and
a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines and which, in a first erase operation, erases an n number of memory cells (n is a natural number equal to or larger than
2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation at a first verify level, finds the number of cells k (k≦
n) (k is a natural number equal to or larger than
1) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out a second erase operation using the second erase voltage.
5 Assignments
0 Petitions
Accused Products
Abstract
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
-
Citations
20 Claims
-
1. A semiconductor memory device comprising:
-
a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines and which, in a first erase operation, erases an n number of memory cells (n is a natural number equal to or larger than
2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation at a first verify level, finds the number of cells k (k≦
n) (k is a natural number equal to or larger than
1) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out a second erase operation using the second erase voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A semiconductor memory device comprising:
-
a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines and which, in an erase operation, erases said plurality of memory cells simultaneously, and verifies the threshold voltage of a memory cell selected by a specific one of the word lines using a first verify level, the first verify level being shifted by a second verify level in verifying all the word line simultaneously. - View Dependent Claims (11, 12)
-
-
13. A semiconductor memory device comprising:
-
a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines, wherein, in an erase operation, the control circuit erases said plurality of memory cells connected to n word lines of the plurality of word lines simultaneously, and carries out a verify operation to determine whether the threshold voltage of a memory cell selected by a specific word line of the n word lines has reached a threshold level in the erase operation using a first verify level. - View Dependent Claims (14, 15, 16)
-
-
17. A semiconductor memory device comprising:
-
a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix; and a control circuit which controls the potentials of said plurality of word lines and said plurality of bit lines, wherein, in an erase operation, the control circuit erases said plurality of memory cells connected to n word lines of the plurality of word lines simultaneously and then performs a write operation on said plurality of memory cells connected to the n word lines simultaneously, and carries out a verify operation to determine whether the threshold voltage of a memory cell selected by a specific word line of the n word lines has reached a threshold level using a first verify level. - View Dependent Claims (18, 19, 20)
-
Specification