Closed galois field combination

• US 7,995,757 B2
• Filed: 05/31/2007
• Issued: 08/09/2011
• Est. Priority Date: 05/31/2007
• Status: Active Grant

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Michaels, Alan J., Chester, David B.
• Primary Examiner(s): Zand; Kambiz
• Assistant Examiner(s): Durham; Imhotep
• Application Number:
  US11/756,086
• Publication Number:
  US 20090044080A1
• Time in Patent Office: 1,531 Days
• Field of Search: None
• US Class Current: 380/255
• CPC Class Codes: G06F 7/725 over elliptic curves

Abstract

A method is provided for combining two or more input sequences in a communications system to increase a repetition period of the input sequences in a resource-efficient manner. The method includes a receiving step, a mapping step, and a generating step. The receiving step involves receiving a first number sequence and a second number sequence, each expressed in a Galois field GF[p^k]. The mapping step involves mapping the first and second number sequences to a Galois extension field GF[p^k+1]. The generating step involves generating an output sequence by combining the first number sequence with the second number sequence utilizing a Galois field multiplication operation in the Galois extension field GF[p^k+1]. p is a prime number. k is an integer. p^k+1 defines a finite field size of the Galois extension field GF[p^k+1].

Claims

1. A method for combining at least two input sequences in a communications system to increase a repetition period of the at least two input sequences in a resource efficient manner, comprising:

receiving, by an electronic circuit, a first number sequence and a second number sequence, each expressed in a Galois field GF[p^k];

mapping, by said electronic circuit, said first number sequence and said second number sequence to a Galois extension field GF[p^k+1]; and

generating, by said electronic circuit, an output sequence by combining said first number sequence with said second number sequence utilizing a Galois field multiplication operation in said Galois extension field GF[p^k+1], where p is a prime number, k is an integer value, and p^k+1 defines a finite field size of said Galois extension field GF[p^k+1].

2. The method according to claim 1, wherein p^k is selected to be a prime number defining a finite field size of said Galois field GF[p^k].

3. The method according to claim 1, further comprising expressing, by said electronic circuit, said first number sequence and said second number sequence in a p-adic number system representation prior to said receiving step.

4. The method according to claim 1, further comprising expressing, by said electronic circuit, said first number sequence and said second number sequence in a mixed-radix number system representation prior to said receiving step.

5. The method according to claim 1, wherein each of said first number sequence and said second number sequence are selected to be comprised of at least two digits expressed in a weighted number system.

6. The method according to claim 1, wherein said generating step further comprises combining said first number sequence and said second number sequence by selectively performing a plurality of Galois field multiplication operations using a distinct, subset of digits from each of said first number sequence and said second number sequence.

7. The method according to claim 1, wherein said first number sequence is selected to be payload data or a random number sequence.

8. The method according to claim 1, wherein said second number sequence is selected to be a pseudo random number sequence or a pseudo-chaotic random number sequence.

9. The method according to claim 1, wherein a plurality of input sequences are selected to be random number sequences having a known mathematical relationship and wherein said plurality of input sequences are combined with said first number sequence.

10. The method according to claim 1, wherein said mapping step further comprises performing an Affine transformation of said first number sequence and said second number sequence.

11. The method according to claim 10, wherein said Affine transformation is selected to be a function of time.

12. A closed Galois field cryptographic (CGFC) system, comprising:

at least one electronic circuit configured to;

receive a first number sequence and a second number sequence, each expressed in a Galois field GF[p^k];

map said first number sequence and said second number sequence to a Galois extension field GF[p^k+1]; and

generate an output sequence by combining said first number sequence with said second number sequence utilizing a Galois field multiplication operation in said Galois extension field GF[p^k+1], where p is a prime number, k is an integer value, and p^k+1 defines a finite field size of said Galois extension field GF[p^k+1].

13. The CGFC system according to claim 12, wherein p^k is selected to be a prime number defining a finite field size of a Galois field GF[p^k].

14. The CGFC system according to claim 12, wherein said first number sequence and said second number sequence are expressed in a p-adic number system representation or a mixed-radix number system representation.

15. The CGFC system according to claim 12, wherein each of said first number sequence and said second number sequence are selected to be comprised of at least two digits expressed in a weighted number system.

16. The CGFC system according to claim 12, wherein said electronic circuit is further configured to combine said first number sequence and said second number sequence by selectively performing a plurality of Galois field multiplication operations using distinct subset of digits from each of said first number sequence and said second number sequence.

17. The CGFC system according to claim 12, wherein said first number sequence is payload data or a random number sequence.

18. The CGFC system according to claim 12, wherein said second number sequence is a pseudo random number sequence or a pseudo-chaotic random number sequence.

19. The CGFC system according, to claim 12, wherein said electronic circuit is further configured to combine a plurality of input sequences with said first number sequence, wherein said plurality of input sequences are random number sequences having a known mathematical relationship.

20. The CGFC system according to claim 12, wherein said electronic circuit is further configured to perform an Affine transformation of said first number sequence and said second number sequence.