Semiconductor device

• US 7,995,984 B2
• Filed: 10/03/2008
• Issued: 08/09/2011
• Est. Priority Date: 11/21/2007
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sakurai, Satoshi, Yamaura, Masashi, Maehara, Takayuki, Tsutsui, Takayuki, Arai, Reiichi, Kudaishi, Tomoaki
• Primary Examiner(s): Le; Nhan
• Application Number:
  US12/244,908
• Publication Number:
  US 20090130996A1
• Time in Patent Office: 1,040 Days
• Field of Search: 455/307, 455/323, 455/333, 455/334
• US Class Current: 455/333
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

The present invention aims to reduce an exclusively-possessed area of each of bonding wires mounted over a wiring board, for coupling a power amplifying unit of a semiconductor chip and an antenna switch of a second semiconductor chip in a semiconductor device that configures an RF module. In the RF module, the first semiconductor chip and the second semiconductor chip are mounted side by side in a central area of the wiring board. The first semiconductor chip is formed with amplifier circuits and a control circuit and comprises a silicon substrate or a compound semiconductor substrate. On the other hand, the second semiconductor chip is formed with an antenna switch and comprises the silicon substrate or compound semiconductor substrate. Pads of the first semiconductor chip and pads of the second semiconductor chip are respectively electrically coupled to one another. This coupling is carried out by the bonding wires formed in the surface of the wiring board and the bonding wires formed inside the wiring board.

Claims

1. A semiconductor device comprising:

(a) a wiring board having a multilayered wiring structure;

(b) a first semiconductor chip mounted over the wiring board, including a power controller for controlling power amplification of a signal; and

(c) a second semiconductor chip mounted over the wiring board, including an antenna switch,

wherein electrical coupling between the power controller of the first semiconductor chip and the antenna switch of the semiconductor chip is conducted by (d1) a plurality of first pads formed in the first semiconductor chip, a plurality of first wires respectively electrically coupled to the first pads, and a plurality of bonding wires which have one ends respectively electrically coupled to the first wires and which are formed in the wiring board, and (d2) a plurality of second wires respectively electrically coupled to the other ends of the bonding wires and a plurality of second pads respectively electrically coupled to the second wires and formed in the second semiconductor chip, and

wherein the bonding wires include a plurality of first bonding wires formed in the surface of the wiring board and a plurality of second bonding wires formed inside the wiring board.

2. The semiconductor device according to claim 1, wherein the bonding wires are formed in the wiring board so as to be interposed between the first semiconductor chip and the second semiconductor chip.

3. The semiconductor device according to claim 2,

wherein the first pads are arranged at a first side of the first semiconductor chip,

wherein the second pads are arranged at a second side of the second semiconductor chip, and

wherein the arrangement of the first pads and the arrangement of the second pads are provided side by side so as to interpose the bonding wires therebetween.

4. The semiconductor device according to claim 1, wherein the second bonding wires include wires for transmitting signals sent from the first semiconductor chip to the second semiconductor chip.

5. The semiconductor device according to claim 4, wherein the second bonding wires include a wire for transmitting a changeover control signal for controlling switching of the antenna switch formed in the second semiconductor chip.

6. The semiconductor device according to claim 5, wherein the antenna switch includes a field effect transistor, and the changeover control signal is of a signal which is applied to a gate electrode of the field effect transistor thereby to control turning ON/OFF of the field effect transistor.

7. The semiconductor device according to claim 6, wherein the field effect transistor is a high electron mobility transistor.

8. The semiconductor device according to claim 4, wherein the second bonding wires include a power wire for supplying power to the antenna switch formed in the second semiconductor chip.

9. The semiconductor device according to claim 1, wherein the second bonding wires include wires for transmitting signals sent from the second semiconductor chip to the first semiconductor chip.

10. The semiconductor device according to claim 1, wherein the first semiconductor chip is provided with a power amplifying unit for amplifying power of each signal in addition to the power controller for controlling the power amplification of the signal.

11. The semiconductor device according to claim 10,

wherein the second semiconductor chip has a detection unit for detecting the power of the signal amplified by the power amplifying unit,

wherein the power controller formed in the first semiconductor chip controls power amplification of the signal, based on a detection signal from the detection unit formed in the second semiconductor chip, and

wherein the second bonding wires include a wire for transmitting the detection signal.

12. The semiconductor device according to claim 10, wherein the first semiconductor chip includes a plurality of power amplifying units for amplifying power of signals different in frequency band in addition to the power controller.

13. The semiconductor device according to claim 12,

wherein the power amplifying units includes a first power amplifying unit for amplifying a first signal lying in a first frequency band and a second power amplifying unit for amplifying a second signal lying in a band different from the first frequency band,

wherein the antenna switch has a first selector switch for transmitting either the amplified first signal or the amplified second signal from an antenna and a second selector switch for inputting the signal received by the antenna to a receiving circuit,

wherein the first selector switch is controlled by a first changeover control signal outputted from the power controller and the second selector switch is controlled by a second changeover control signal outputted from the power controller, and

wherein the second bonding wires include a wire for transferring the first changeover control signal, whereas the first bonding wires include a wire for transferring the second changeover control signal.

14. The semiconductor device according to claim 10,

wherein the wiring board is provided with (e) a matching circuit for taking impedance matching and (f) a selection circuit for causing signals lying plural frequency bands to signals lying in a frequency band in a specific range to pass therethrough,

wherein the output of the power amplifying unit formed in the first semiconductor chip is inputted to the matching circuit,

wherein the output of the matching circuit is inputted to the selection circuit,

wherein the output of the selection output is inputted to the antenna switch formed in the second semiconductor chip, and

wherein the output from the antenna switch is transmitted through the antenna.

15. The semiconductor device according to claim 14, wherein the selection circuit is configured using first wires formed in the surface of the wiring board and second wires formed inside the wiring board.

16. The semiconductor device according to claim 14,

wherein the bonding wires are disposed between a first side of the first semiconductor chip over which the first pads are arranged, and a second side of the second semiconductor chip over which the second pads are arranged and which is provided side by side with the first side, in such a manner that the bonding wires are aligned in the direction parallel to the first side and the second side,

wherein a width in which the bonding wires are disposed side by side is smaller than either a width of the first side or a width of the second side,

wherein a plurality of third pads for outputting the power sent from the power amplifying unit are formed at a third side which intersects with the first side of the first semiconductor chip,

wherein the third pads and the matching circuit formed over the wiring board are respectively coupled by a plurality of third wires,

wherein a plurality of fourth pads coupled to the antenna switch are formed at a fourth side which intersects with the second side of the second semiconductor chip,

wherein the fourth pads and the selection circuit formed over the wiring board are respectively coupled by a plurality of fourth wires,

wherein the first wires and the third wires are placed in a layout relationship in which the first and third wires are not brought into contact with one another and intersect on a plane basis where the first and third wires extend, and

wherein the second wires and the fourth wires are placed in a layout relationship in which the second and fourth wires are not brought into contact with one another and intersect on a plane basis where the second and fourth wires extend.

17. The semiconductor device according to claim 16,

wherein the angle which each of the first wires forms with each of the third wires ranges from 45°

or more to 135°

or less, and

wherein the angle which each of the second wires forms with each of the fourth wires ranges from 45°

or more to 135°

or less.

18. The semiconductor device according to claim 1,

wherein the bonding wires are disposed between a first side of the first semiconductor chip over which the first pads are arranged, and a second side of the second semiconductor chip over which the second pads are arranged and which is parallel to the first side, in such a manner that the bonding wires are aligned in the direction parallel to the first side and the second side, and

wherein a width in which the bonding wires are disposed side by side is smaller than either a width of the first side or a width of the second side.

19. The semiconductor device according to claim 18,

wherein the bonding wires include the first bonding wires, and

wherein the first bonding wire disposed on the end side of the first or second side, of the first bonding wires is longer in wiring length than the first bonding wire disposed on the central side of the first or second side.

20. The semiconductor device according to claim 19, wherein the length of the first wire coupled to the first bonding wire disposed on the end side of the first side, of the first wires is shorter than the length of the first wire coupled to the first bonding wire disposed on the central side of the first side.

21. The semiconductor device according to claim 19, wherein the length of the second wire coupled to the first bonding wire disposed on the end side of the second side, of the second wires is longer than the length of the second wire coupled to the first bonding wire disposed on the central side of the second side.

22. The semiconductor device according to claim 18,

wherein the bonding wires include the first bonding wires and the second bonding wires,

wherein the first bonding wires are disposed from the central side of the first or second side to the end side of the first or second side, and

wherein the second boding wires are disposed on the central side of the first or second side and are not disposed on the end side of the first or second side.

23. The semiconductor device according to claim 18, wherein a layout in which the bonding wires are disposed side by side, is not symmetrical with respect to a center line which passes through the center of the first side or a center line which passes through the center of the second side.

24. The semiconductor device according to claim 23,

wherein the wiring board includes a first matching circuit which is electrically coupled to a first power amplifying unit for amplifying power of a first signal lying in a first frequency band and which takes impedance matching to transfer the power efficiently, a first selection circuit which is electrically coupled to the first matching circuit and selects a signal lying in a frequency band in a specific range from signals lying in a plurality of frequency bands, a second matching circuit which is electrically coupled to a second power amplifying unit for amplifying power of a second signal lying in a second frequency band higher than the first signal of the first frequency band and takes impedance matching to transfer the power efficiently, and a second selection circuit which is electrically coupled to the second matching circuit and selects a signal lying in a specific frequency band from signals lying in a plurality of frequency bands,

wherein the first matching circuit and the first selection circuit are disposed in the direction which intersects with the direction in which the first semiconductor chip and the second semiconductor chip are aligned, and the first matching circuit and the first selection circuit are disposed on the side opposite to the second matching circuit and the second selection circuit through the first semiconductor chip and the second semiconductor chip,

wherein a layout in which the bonding wires are disposed side by side, is placed with being shifted in the direction in which the second matching circuit and the second selection circuit are formed, and

wherein space is ensured on the formation side of the first matching circuit and the first selection circuit.