Messaging mechanism for inter processor communication

• US 7,996,574 B2
• Filed: 05/03/2007
• Issued: 08/09/2011
• Est. Priority Date: 12/18/1998
• Status: Expired due to Fees

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Wang, Yao, Gupta, Reema, Tringale, Alesia
• Primary Examiner(s): Colin; Carl
• Assistant Examiner(s): THIAW, CATHERINE B
• Application Number:
  US11/800,091
• Publication Number:
  US 20070271572A1
• Time in Patent Office: 1,559 Days
• Field of Search: 714 48- 57, 710/7
• US Class Current: 710/7
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Claims

1. An apparatus for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system, the apparatus comprising:

a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache;

a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines; and

in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline;

wherein;

the apparatus further comprises a plurality of assembler/disassembler mechanisms, each assembler/disassembler mechanism coupling to one or more pipelines;

each pipeline further comprises;

a first first-in first-out (FIFO) buffer, wherein the separated user data from the protocol engine is temporarily stored in the first FIFO buffer before being transmitted to an assembler/disassembler mechanism in a first direction for a write operation;

a second FIFO buffer, configured to receive additional data from the assembler/disassembler mechanism and to transmit the additional data to the protocol engine in a second, opposite, direction for a read operation;

a receive frame memory, configured to receive frame header data from the protocol engine; and

a transmit frame memory, configured to transmit frame header data to the protocol engine;

the protocol engine is further configured to compute error detection information for the user data;

the user data is stored in the first FIFO buffer together with the error detection information; and

each assembler/disassembler mechanism is configured to;

receive user data from the first FIFO buffer;

generate error detection information for the user data; and

output, based on the generated error detection information and the error detection information stored in the first FIFO buffer, a signal indicating whether the user data has been received in proper sequence from the first FIFO buffer.

2. An apparatus as in claim 1 wherein each assembler/disassembler mechanism is further configured to accumulate user data until a threshold quantity of data is accumulated for an efficient transfer and subsequently pass the accumulated data along the pipeline in a single burst.

3. A method for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system, the method comprising:

connecting the host ESCON I/O interface to the cache over at least 4 pipelines, each pipeline being controlled by one of a plurality of line processors;

placing in each pipeline a protocol engine for distinguishing user data from frame header data;

separating the user data from the frame header data, at a protocol engine of the plurality of protocol engines, for transport over the pipeline;

calculating error detection information for the user data at a protocol engine of the plurality of protocol engines;

receiving, at a receive frame memory, frame header data from the protocol engine;

temporarily storing the separated user data for a write operation together with the error detection information in a first first-in first-out (FIFO) buffer associated with the pipeline;

receiving, in a first direction, at an assembler/disassembler mechanism, the separated user data from the first FIFO buffer;

generating, at the assembler/disassembler mechanism, error detection information for the separated user data;

outputting, based on the generated error detection information and the error detection information stored in the first FIFO buffer, a signal indicating whether the user data has been received in proper sequence from the first FIFO buffer;

transmitting, from a transmit frame memory, frame header data to the protocol engine; and

transmitting, for a read operation in a second, opposite, direction, from a second FIFO buffer, additional data to the protocol engine.

4. A method as in claim 3 wherein the method further comprises, at the assembler/disassembler mechanism, accumulating user data until a threshold quantity of data is accumulated for an efficient transfer and subsequently passing the accumulated data along the pipeline in a single burst.