Cross bar multipath resource controller system and method
First Claim
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1. A system comprising:
- a plurality of memory resources;
a plurality of peripheral resources;
a plurality of processors;
a memory controller coupled to said plurality of processors and said plurality of memory resources, wherein said memory controller comprises a first resource controller operable to control access by said plurality of processors to said plurality of memory resources using a hardware semaphore unit, wherein said first resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of memory resources, wherein said memory controller is further operable to enable each processor of said plurality of processors to simultaneously access a respective portion of a memory resource of said plurality of memory resources, and wherein said memory controller is further operable to enable each of said plurality of processors to have priority access to a respective instruction memory of a plurality of instruction memories; and
a peripheral controller coupled to said plurality of processors and said plurality of peripheral resources, wherein said peripheral controller comprises a second resource controller operable to control access by said plurality of processors to said plurality of peripheral resources using said hardware semaphore unit, and wherein said second resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of peripheral resources.
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Abstract
A cross bar multipath resource controller system and method permit multiple processors in a computer system to access various resource of the computer system, such as memory or peripherals, with zero blocking access. In particular, each processor has its own bus so that the processors can each independently access different resources in the computer system simultaneously.
53 Citations
24 Claims
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1. A system comprising:
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a plurality of memory resources; a plurality of peripheral resources; a plurality of processors; a memory controller coupled to said plurality of processors and said plurality of memory resources, wherein said memory controller comprises a first resource controller operable to control access by said plurality of processors to said plurality of memory resources using a hardware semaphore unit, wherein said first resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of memory resources, wherein said memory controller is further operable to enable each processor of said plurality of processors to simultaneously access a respective portion of a memory resource of said plurality of memory resources, and wherein said memory controller is further operable to enable each of said plurality of processors to have priority access to a respective instruction memory of a plurality of instruction memories; and a peripheral controller coupled to said plurality of processors and said plurality of peripheral resources, wherein said peripheral controller comprises a second resource controller operable to control access by said plurality of processors to said plurality of peripheral resources using said hardware semaphore unit, and wherein said second resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of peripheral resources. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A component for negotiating access to a plurality of shared resources, said component comprising:
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a memory controller coupled to said plurality of processors and said plurality of memory resources, wherein said memory controller comprises a first resource controller operable to control access by said plurality of processors to said plurality of memory resources using a hardware semaphore unit, wherein said first resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of memory resources, wherein said memory controller is further operable to enable each processor of said plurality of processors to simultaneously access a respective portion of a memory resource of said plurality of memory resources, and wherein said memory controller is further operable to enable each of said plurality of processors to have priority access to a respective instruction memory of a plurality of instruction memories; and a peripheral controller coupled to said plurality of processors and said plurality of peripheral resources, wherein said peripheral controller comprises a second resource controller operable to control access by said plurality of processors to said plurality of peripheral resources using said hardware semaphore unit, and wherein said second resource controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of peripheral resources. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A controller for negotiating access to a plurality of shared resources, said controller comprising:
a resource arbitration controller operable to control access by said plurality of processors to said plurality of shared resources using a hardware semaphore unit, wherein said resource arbitration controller is further operable to implement respective buses for coupling said plurality of processors to said plurality of shared resources, wherein said resource arbitration controller is further operable to enable each processor of said plurality of processors to simultaneously access a respective portion of a shared resource of said plurality of shared resources, and wherein said resource arbitration controller is further operable to enable each of said plurality of processors to have priority access to a respective instruction memory of a plurality of instruction memories. - View Dependent Claims (20, 21, 22, 23, 24)
Specification