High performance pseudo dynamic 36 bit compare
First Claim
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1. A set associative cache memory address comparator comprising in combination:
- a plurality of comparator macros each comprised of static logic elements;
a bus to couple a different segment of said cache memory address and a bus to couple a corresponding segment of a cache memory tag address to an input of each of said plurality of comparator macros;
each of said plurality of comparator macros generating a hit output if there is a bit by bit comparison between the cache memory segment and the tag memory segment coupled to its input;
a dynamic logic gate with an input from an output of each of said plurality of comparator macros;
said dynamic logic gate generating a cache select signal if the output state from each said plurality of comparator macros is said predetermined binary output state.
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Abstract
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.
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Citations
20 Claims
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1. A set associative cache memory address comparator comprising in combination:
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a plurality of comparator macros each comprised of static logic elements; a bus to couple a different segment of said cache memory address and a bus to couple a corresponding segment of a cache memory tag address to an input of each of said plurality of comparator macros; each of said plurality of comparator macros generating a hit output if there is a bit by bit comparison between the cache memory segment and the tag memory segment coupled to its input; a dynamic logic gate with an input from an output of each of said plurality of comparator macros; said dynamic logic gate generating a cache select signal if the output state from each said plurality of comparator macros is said predetermined binary output state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for generating a cache select signal in a set associative cache memory, including the steps of:
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dividing a cache memory address into a plurality of cache address memory segments; dividing a cache tag address into said plurality of tag address memory segments; comparing each of said cache memory address segments with each corresponding ones of said tag memory address segments in a static comparison process to generate a hit output from each comparison; combining each result of the comparing step in a dynamic logic process to generate a cache select signal if each result of the comparing step is said hit output. - View Dependent Claims (11, 12, 13)
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14. A method for operation of a cache memory address comparator comprising in combination the steps of:
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dividing a cache memory address into a plurality of cache memory address segments; dividing a cache tag address into said plurality of tag memory address segments; statically comparing each of said cache memory address segments with each corresponding ones of said tag memory address segments process to generate a hit output from each comparison; dynamically combining each hit output to generate a cache select signal if each result of the comparing step is said hit output. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification