Digital locked loop on channel tagged memory requests for memory optimization
First Claim
1. A method for performing memory optimization on a memory, the method comprising:
- receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests, such that a series of read/write requests having matching identifiers are associated and related with one another;
measuring arrival times of the read/write requests assigned to each of the identifiers;
determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers;
creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests;
using the real-time schedule to determine idle periods during which none of the read/write requests will be received; and
performing opportunistic functions in the memory during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.
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Accused Products
Abstract
A method and system for performing memory optimization. The method includes receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods where none of the read/write requests will be received; and performing opportunistic functions during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.
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Citations
25 Claims
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1. A method for performing memory optimization on a memory, the method comprising:
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receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests, such that a series of read/write requests having matching identifiers are associated and related with one another; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods during which none of the read/write requests will be received; and performing opportunistic functions in the memory during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory system comprising:
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a memory array comprising physical locations; a translation cache to cache entries mapping logical block addresses to the physical locations of the memory array; and a memory controller to perform memory management functions for the memory array, including; receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests, such that a series of read/write requests having matching identifiers are associated and related with one another; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods during which none of the read/write requests will be received; and performing opportunistic functions during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A non-transitory computer-readable medium containing program instructions for performing memory optimization on a memory, the program instructions for:
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receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests, such that a series of read/write requests having matching identifiers are associated and related with one another; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods during which none of the read/write requests will be received; and performing opportunistic functions in the memory during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.
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Specification