Enhanced microprocessor or microcontroller

• US 7,996,651 B2
• Filed: 06/27/2008
• Issued: 08/09/2011
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Ellison, Ryan Scott, Schroeder, Eric, Delport, Vivien, Smit, Zacharias Marthinus, Julicher, Joseph, Zdenek, Jerrold S., Steedman, Sean
• Primary Examiner(s): PATEL, KAUSHIKKUMAR M
• Application Number:
  US12/147,647
• Publication Number:
  US 20090144511A1
• Time in Patent Office: 1,138 Days
• Field of Search: 711/219, 711/220
• US Class Current: 711/220
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/35 Indirect addressing

Abstract

An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.

Claims

1. An n-bit microprocessor device comprising:

an n-bit central processing unit (CPU);

a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of memory banks, comprising at least two 16-bit indirect memory address registers which are accessible by said CPU across all memory banks;

a bank access unit for coupling said CPU with one of said plurality of memory banks;

a data memory coupled with the CPU; and

a program memory coupled with the CPU,

wherein said indirect memory address registers are operable to access said data memory or program memory and wherein a bit in each of said indirect memory address registers indicates an access to said data memory or to said program memory.

2. The n-bit microprocessor according to claim 1, wherein n=8.

3. The n-bit microprocessor according to claim 1, further comprising at least one virtual register, wherein writing data to said at least one virtual register causes an indirect access using one of said indirect memory address registers to said data memory or to said program memory.

4. The n-bit microprocessor according to claim 3, wherein the at least one virtual register is mapped to each memory bank.

5. The n-bit microprocessor according to claim 1, further comprising at least one virtual register, wherein reading data from said at least one virtual register causes an indirect access using one of said indirect memory address registers to said data memory or to said program memory.

6. The n-bit microprocessor according to claim 5, wherein the at least one virtual register is mapped to each memory bank.

7. The n-bit microprocessor according to claim 5, wherein said microprocessor device comprises two virtual registers and four 8-bit registers forming the two 16-bit indirect memory address registers.

8. The n-bit microprocessor according to claim 1, wherein said data memory is 8-bit wide and said program memory is 14-bit wide.

9. The n-bit microprocessor according to claim 8, wherein one additional bit of a data memory address defines an expanded memory address range used in a debug mode.

10. The n-bit microprocessor according to claim 8, wherein said bit in said indirect memory address register is the most significant bit.

11. A method for operating an n-bit microprocessor device comprising the steps of:

providing an n-bit central processing unit (CPU);

providing a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of memory banks,

providing at least two 16-bit indirect memory address registers which are accessible by said CPU across all memory banks;

providing a bank access unit for coupling said CPU with one of said plurality of memory banks;

providing a data memory coupled with the CPU;

providing a program memory coupled with the CPU; and

performing an indirect addressing using said one of indirect memory address registers to access said data memory or program memory, wherein a bit in each of said indirect memory address registers indicates an access to said data memory or to said program memory, respectively.

12. The method according to claim 11, wherein n=8.

13. The method according to claim 11, further comprising the step of generating an indirect memory write access by writing data to at least one virtual register, wherein the indirect memory access uses one of said indirect memory address registers.

14. The method according to claim 13, wherein said at least one virtual register is memory mapped to all memory banks.

15. The method according to claim 11, further comprising the step of generating an indirect memory read access by reading data from at least one virtual register, wherein the indirect memory read access uses one of said indirect memory address registers.

16. The method according to claim 15, wherein said at least, one virtual register is memory mapped to all memory banks.

17. The method according to claim 15, wherein said microprocessor device comprises two virtual registers and four 8-bit registers forming the two 16-bit indirect memory address registers.

18. The method according to claim 11, wherein said data memory is 8-bit wide and said program memory is 14-bit wide.

19. The method according to claim 18, wherein one additional bit of a data memory address defines an expanded memory address range used in a debug mode.

20. The n-bit microprocessor according to claim 18, wherein said bit in said indirect memory address registers is the most significant bit.