Forward error correction encoding for multiple link transmission compatible with 64B/66B scrambling
First Claim
1. A method of generating a forward error correction (FEC) code for a packet-based digital communications system performed on a serializer/deserializer (SER/DES) link using a self-synchronized scrambler and descrambler, the method comprising:
- applying a first encoding algorithm to a first dataword;
applying a second encoding algorithm to the first dataword;
generating a first checkbit sequence for the first dataword;
appending the checkbit sequence to the first dataword;
scrambling the first dataword at a source node;
transmitting the first dataword on a data transmission link from the source node to a destination node;
descrambling the transmitted first dataword at the destination node;
generating a second checkbit sequence based on the transmitted dataword;
comparing the first checkbit sequence with the second checkbit sequence;
determining whether the received dataword contains a first bit error; and
correcting the first bit error and a first and second replicated bit error.
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Accused Products
Abstract
A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x10+x3+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x6+1.
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Citations
38 Claims
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1. A method of generating a forward error correction (FEC) code for a packet-based digital communications system performed on a serializer/deserializer (SER/DES) link using a self-synchronized scrambler and descrambler, the method comprising:
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applying a first encoding algorithm to a first dataword; applying a second encoding algorithm to the first dataword; generating a first checkbit sequence for the first dataword; appending the checkbit sequence to the first dataword; scrambling the first dataword at a source node; transmitting the first dataword on a data transmission link from the source node to a destination node; descrambling the transmitted first dataword at the destination node; generating a second checkbit sequence based on the transmitted dataword; comparing the first checkbit sequence with the second checkbit sequence; determining whether the received dataword contains a first bit error; and correcting the first bit error and a first and second replicated bit error. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of applying a forward error correction code to a digital signal for transmission on a serializer-deserializer link using a self-synchronized scrambler and descrambler, the method comprising:
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applying a Hamming code to the digital signal from an irreducible polynomial of the form H(x)=x10+x3+1; applying a bit-interleaved parity code to the digital signal of degree n (BIP-n), where n corresponds to the highest order of the polynomial representing the bit-interleaved parity code; generating a first checkbit sequence for the encoded digital signal; appending the first checkbit sequence to the encoded digital signal; scrambling the encoded digital signal and the first checkbit sequence using a 64B/66B scrambling protocol; transmitting the scrambled and encoded digital signal over the serializer-deserializer link; descrambling the transmitted digital signal at a receiver node; generating a second checkbit sequence at the receiver node; comparing the first checkbit sequence with the second checkbit sequence; determining whether the transmitted digital signal contains a first bit error; and correcting the first bit error, a first replicated error and a second replicated error. - View Dependent Claims (16)
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17. A method of building a forward error correction (FEC) code for a packet-based digital communications system using a self-synchronized scrambler, said method comprising the steps of:
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determining the power (n) of a bit interleave parity (BIP-n) code capable of discriminating between all error patterns of a single transmission error and replications thereof generated by said self-synchronized scrambler upon reception of transmitted FEC encoded frames), where n corresponds to the highest order of the polynomial representing the bit-interleaved parity code; determining the power of a polynomial used to generate a Hamming code of a length compatible with the packet size of said packet-based digital communications system; combining said BIP-n code and said Hamming code to form said FEC code and obtain, upon reception of said transmitted FEC encoded frames, a set of unique syndromes for all combinations of said single bit transmission errors and replications; and allowing the FEC code to correct all single transmission errors and their replications by the self-synchronized scrambler while preserving a bit transition density of a physical layer as provided by said scrambler. - View Dependent Claims (18, 19)
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20. A program storage device readable by a processor, tangibly embodying a program of instructions executable by the processor to perform method steps for generating a forward error correction (FEC) code in a packet-based digital communications system using a self-synchronized scrambler and descrambler, said method steps comprising:
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applying a first encoding algorithm to a first dataword; applying a second encoding algorithm to the first dataword; generating a first checkbit sequence for the first dataword; appending the checkbit sequence to the first dataword; scrambling the first dataword at a source node; transmitting the first dataword on a data transmission link from the source node to a destination node; descrambling the transmitted first dataword at the destination node; and generating a second checkbit sequence based on the transmitted dataword; comparing the first checkbit sequence with the second checkbit sequence; determining whether the received dataword contains a first bit error; and correcting the first bit error and correcting a first and second replicated bit error. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A system for generating a forward error correction (FEC) code for a packetized dataword, the system comprising:
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a first encoder adapted to apply a first encoding algorithm to the packetized dataword; a second encoder adapted to apply a second encoding algorithm to the packetized dataword; a scrambler element adapted to apply a scrambling polynomial to the encoded packetized dataword at a source node; a communications channel link adapted to transmit the encoded and scrambled packetized dataword from the source node to a destination node; a descrambler element adapted to apply a descrambling polynomial to the transmitted packetized dataword at the destination node; a decoder element adapted to decode the encoded packetized dataword at a destination node; and an XOR logic element adapted to compare a regenerated checkbit sequence with a transmitted checkbit sequence appended to the transmitted packetized dataword. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38)
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Specification