Signal loss detector for high-speed serial interface of a programmable logic device

• US 7,996,749 B2
• Filed: 07/03/2007
• Issued: 08/09/2011
• Est. Priority Date: 07/03/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ding, Weiqi, Tran, Thungoc M., Wong, Wilson, Shumarayev, Sergey, Hoang, Tim Tri
• Primary Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US11/773,234
• Publication Number:
  US 20090011716A1
• Time in Patent Office: 1,498 Days
• Field of Search: 714/789, 327/231, 375/232
• US Class Current: 714/789
• CPC Class Codes: H04L 25/45 using electronic distributors

Abstract

A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Claims

1. A loss-of-signal detector comprising:

a digital data pattern detector that compares incoming data to at least one predetermined data pattern and provides a first loss-of-signal indication based on whether said incoming data match any one of said at least one predetermined data pattern;

an analog detector that outputs a second loss-of-signal indication based upon presence or absence of a plurality of transitions in said incoming data; and

a decision circuit that outputs a third loss-of-signal indication based on said first and second loss-of-signal indications.

2. The loss-of-signal detector of claim 1 wherein:

when said first loss-of-signal indication indicates that said incoming data do not match any one of said at least one predetermined pattern, said decision circuit outputs said third loss-of-signal indication in a state indicating presence of signal.

3. The loss-of-signal detector of claim 1 wherein:

when said first loss-of-signal indication indicates that said incoming data match one of said at least one predetermined pattern, said decision circuit outputs said third loss-of signal indication based on status of said second loss-of-signal indication.

4. The loss-of-signal detector of claim 3 wherein:

when said second loss-of-signal indication indicates presence of a plurality of transitions in said incoming data, said decision circuit outputs said third loss-of-signal indication in a state indicating presence of signal; and

when said second loss-of-signal indication indicates absence of a plurality of transitions in said incoming data, said decision circuit outputs said third loss-of-signal indication in a state indicating loss of signal.

5. The loss-of-signal detector of claim 1 wherein:

said analog detector comprises a shift register coupled to a source of signal indicating presence of transitions; and

said incoming data are provided to a clock input of said shift register;

whereby;

transitions in said incoming data shift said signal indicating presence of transitions to an output of said shift register.

6. The loss-of-signal detector of claim 5 wherein said analog signal detector further comprises an analog amplifier through which said incoming data are provided to said clock input of said shift register.

7. The loss-of-signal detector of claim 1 wherein said decision circuit comprises an AND gate to which said first and second loss-of-signal indications are provided as inputs.

8. The loss-of-signal detector of claim 7 further comprising a respective register through which said respective first and second loss-of-signal indications are provided to said AND gate as inputs.

9. The loss-of-signal detector of claim 8 wherein one of said registers inverts its respective one of said first and second loss-of-signal indications.

10. The loss-of-signal detector of claim 9 wherein said second loss-of-signal indication is inverted by said one of said registers.

11. A serial interface comprising the loss-of-signal detector of claim 1.

12. A programmable logic device comprising the serial interface of claim 11.

13. A printed circuit board on which is mounted a programmable logic device as defined in claim 12.

14. The printed circuit board defined in claim 13 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

15. The printed circuit board defined in claim 14 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

16. A method for detecting loss-of-signal in a serial data interface, said method comprising:

comparing even samples of incoming data to a threshold using a first comparator and odd samples of said incoming data to said threshold using a second comparator, to generate a pattern of incoming data;

comparing said pattern of incoming data to at least one predetermined data pattern, and providing a first loss-of-signal indication based on whether said incoming data match any one of said at least one predetermined data pattern;

generating a second loss-of-signal indication based upon presence or absence of a plurality of transitions in said incoming data; and

outputting a third loss-of-signal indication based on said first and second loss-of-signal indications.

17. The loss-of-signal detection method of claim 16 wherein:

when said first loss-of-signal indication indicates that said incoming data do not match any one of said at least one predetermined pattern, said third loss-of-signal indication indicates presence of a signal.

18. The loss-of-signal detection method of claim 16 wherein:

when said first loss-of-signal indication indicates that said incoming data match one of said at least one predetermined pattern, said third loss-of signal indication is based on a status of said second loss-of-signal indication.

19. The loss-of-signal detection method of claim 18 wherein:

when said second loss-of-signal indication indicates presence of a plurality of transitions in said incoming data, said third loss-of-signal indication indicates presence of a signal; and

when said second loss-of-signal indication indicates absence of a plurality of transitions in said incoming data, said third loss-of-signal indication indicates loss of a signal.

20. A loss-of-signal detector for use with a serial data interface for which there is at least one suspect data pattern that is, at different times, (a) a legal pattern and (b) an indication of signal loss, said loss-of-signal detector comprising:

a digital data pattern detector that (1) compares incoming data to at least one predetermined data pattern and (2) provides a first loss-of-signal indication based on whether said incoming data match any one of said at least one predetermined data pattern;

an analog detector that outputs a second loss-of-signal indication based upon presence or absence of a plurality of transitions in said incoming data; and

a decision circuit that outputs a third loss-of-signal indication based on said first and second loss-of-signal indications.