Method for the translation of programs for reconfigurable architectures
First Claim
1. A method of translating high-level language code into a plurality of executable configuration definitions for data processing on a reconfigurable processor chip that includes an arrangement including (a) a plurality of configurable elements, (b) a configurable interconnect adapted for interconnecting the plurality of configurable elements, and (c) memories, wherein memories are also provided external to said arrangement, the method comprising:
- constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed;
assigning memories to the complex combinatory network for storage of operand data and result data; and
generating, by a computer processor, the plurality of executable configuration definitions based on the finite automaton and the memory assignments;
wherein the plurality of executable configuration definitions define (a) configurations of at least one of the configurable interconnect and the plurality of configurable elements for performing the computation, and (b) configurations of the at least one of the configurable interconnect and the plurality of configurable elements for external memory accesses for providing a transfer of at least one of the operand data and result data as data from an external memory to a memory of said arrangement, the configurations for performing the computation being separate from the configurations for external memory accesses such that the configurations for performing the computation and the configurations for external memory accesses are scheduled for execution on the processor chip at different times.
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Abstract
A method for advantageously translating high-level language codes for data processing using a reconfigurable architecture, memories addressable internally from within said reconfigurable architecture, and memories external to said reconfigurable architecture, may include constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed, assigning memories to the network for storage of operands and results, and separating external memory accesses for providing a transfer of at least one of operands and results as data from an external memory to a memory addressable internally by the reconfigurable architecture.
611 Citations
80 Claims
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1. A method of translating high-level language code into a plurality of executable configuration definitions for data processing on a reconfigurable processor chip that includes an arrangement including (a) a plurality of configurable elements, (b) a configurable interconnect adapted for interconnecting the plurality of configurable elements, and (c) memories, wherein memories are also provided external to said arrangement, the method comprising:
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constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed; assigning memories to the complex combinatory network for storage of operand data and result data; and generating, by a computer processor, the plurality of executable configuration definitions based on the finite automaton and the memory assignments; wherein the plurality of executable configuration definitions define (a) configurations of at least one of the configurable interconnect and the plurality of configurable elements for performing the computation, and (b) configurations of the at least one of the configurable interconnect and the plurality of configurable elements for external memory accesses for providing a transfer of at least one of the operand data and result data as data from an external memory to a memory of said arrangement, the configurations for performing the computation being separate from the configurations for external memory accesses such that the configurations for performing the computation and the configurations for external memory accesses are scheduled for execution on the processor chip at different times. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A method of enabling processing of data according to a high-level language code for data processing on a reconfigurable processor chip that includes an arrangement including (a) a plurality of configurable elements, (b) a configurable interconnect adapted for interconnecting the plurality of configurable elements, and (c) memories, wherein memories are also provided external to said arrangement, the method comprising:
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based on the high-level language code, constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed; assigning memories to the complex combinatory network for storage of operand data and result data; and generating, by a computer processor, a plurality of executable configuration definitions based on the finite automaton and the memory assignments, the configuration definitions defining (a) configurations of at least one of the configurable interconnect and the plurality of configurable elements for transferring processing data between an external memory and a memory of said arrangement, and (b) configurations of the at least one of the configurable interconnect and the plurality of configurable elements for performing functions defined by said high-level language code, wherein the configurations for transferring processing data are separate from the configurations for performing functions, such that the configurations for transferring processing data and the configurations for performing functions are scheduled for execution on the processor chip at different times. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A method of executing code for data processing on a reconfigurable processor chip that includes an arrangement including (a) a plurality of configurable elements, (b) a configurable interconnect adapted for interconnecting the plurality of configurable elements, and (c) memories, wherein memories are also provided external to said arrangement, the method comprising:
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generating, by a computer processor, a first executable configuration definition that defines a configuration of at least one of the configurable interconnect and the plurality of configurable elements for performing individual functions on the reconfigurable processor chip using memories assigned for storage of operand data and result data, performance of the individual functions including addressing part of the memories assigned for storage of operand data and result data internally from within said arrangement; generating, by the processor, a second executable configuration definition that defines a configuration of at least one of the configurable interconnect and plurality of configurable elements for external memory accesses to transfer processing data between an external memory and a memory of said arrangement; scheduling executions of the configurations defined by the first and second executable configuration definitions for performance at different times; performing the individual functions using the processor chip configured according to the configuration defined by the first executable configuration definition until a time period scheduled for the configuration of the second executable configuration definition; and at the time scheduled for the configuration of the second executable configuration definition, reconfiguring the processor chip from the configuration defined by the first executable configuration definition to the configuration defined by the second executable configuration definition. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80)
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Specification