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Method for the translation of programs for reconfigurable architectures

  • US 7,996,827 B2
  • Filed: 08/16/2002
  • Issued: 08/09/2011
  • Est. Priority Date: 08/16/2001
  • Status: Active Grant
First Claim
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1. A method of translating high-level language code into a plurality of executable configuration definitions for data processing on a reconfigurable processor chip that includes an arrangement including (a) a plurality of configurable elements, (b) a configurable interconnect adapted for interconnecting the plurality of configurable elements, and (c) memories, wherein memories are also provided external to said arrangement, the method comprising:

  • constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed;

    assigning memories to the complex combinatory network for storage of operand data and result data; and

    generating, by a computer processor, the plurality of executable configuration definitions based on the finite automaton and the memory assignments;

    wherein the plurality of executable configuration definitions define (a) configurations of at least one of the configurable interconnect and the plurality of configurable elements for performing the computation, and (b) configurations of the at least one of the configurable interconnect and the plurality of configurable elements for external memory accesses for providing a transfer of at least one of the operand data and result data as data from an external memory to a memory of said arrangement, the configurations for performing the computation being separate from the configurations for external memory accesses such that the configurations for performing the computation and the configurations for external memory accesses are scheduled for execution on the processor chip at different times.

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