Method of fabricating a high-voltage transistor with an extended drain structure

• US 7,998,817 B2
• Filed: 04/18/2009
• Issued: 08/16/2011
• Est. Priority Date: 09/07/2001
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Loke; Steven
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US12/386,392
• Publication Number:
  US 20090233407A1
• Time in Patent Office: 850 Days
• Field of Search: 438/197, 438/268, 438/270, 438/238
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/925 Fluid growth doping control, e.g. delta doping

Abstract

A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Claims

1. A method comprising:

forming, in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls, the mesa comprising an epitaxial layer formed with a doping concentration that is lower near an upper portion, as compared to a lower portion, of the epitaxial layer;

partially filling each of the trenches with a dielectric material that covers the first and second sidewalls;

filling a remaining portion of the trenches with a conductive material to form first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from near a bottom of the mesa to a top surface of the semiconductor substrate;

forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the lower portion of the mesa; and

forming a gate embedded within the dielectric material adjacent the body region, the gate being insulated from the body region and the first and second field plates.

2. The method of claim 1 further comprising:

forming a drain region of the first conductivity type at the bottom of the mesa, the drain region being connected to the drift region;

forming a source electrode connected to the source region; and

forming a drain electrode connected to the substrate.

3. The method of claim 1 wherein the first conductivity type is n-type.

4. The method of claim 1 wherein the drift region has a linearly graded doping profile.

5. A method comprising:

forming, in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls, the mesa comprising an epitaxial layer formed with a linearly graded doping profile;

partially filling each of the trenches with a dielectric material that covers the first and second sidewalls;

filling a remaining portion of the trenches with a conductive material to form first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from near a bottom of the mesa to a top surface of the semiconductor substrate;

forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the lower portion of the mesa; and

forming a gate embedded within the dielectric material adjacent the body region, the gate being insulated from the body region and the first and second field plates.

6. The method of claim 5 further comprising:

forming a drain region of the first conductivity type at the bottom of the mesa, the drain region being connected to the drift region;

forming a source electrode connected to the source region; and

forming a drain electrode connected to the substrate.

7. The method of claim 5 wherein the first conductivity type is n-type.

8. The method of claim 5 wherein the linearly graded doping profile of the epitaxial layer is formed such that the mesa has a doping concentration that is lower near the body region, as compared to a lower portion of the epitaxial layer.