Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

• US 7,999,295 B2
• Filed: 12/17/2008
• Issued: 08/16/2011
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hsieh, Kuang-Yeu, Lai, Erh-Kun, Lue, Hang-Ting
• Primary Examiner(s): Nhu; David
• Application Number:
  US12/337,289
• Publication Number:
  US 20090096017A1
• Time in Patent Office: 972 Days
• Field of Search: 257/288, 257/296, 257/347, 257/615, 257/616, 257/649, 257/780, 257/E21.17, 257/E21.21, 257/E21.32, 257/E21.293, 257/E21.267, 257/E21.411, 257/E21.646
• US Class Current: 257/296
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.

Claims

1. A non-volatile memory device, comprising:

an insulator;

a plurality of bit lines and a plurality of word lines disposed over the insulator;

a plurality of memory elements disposed between the plurality of bit lines and the plurality of word lines;

a plurality of source/drain regions formed in each of the plurality of bit lines; and

active regions in the plurality of bit lines beneath the plurality of word lines, and wherein the source/drain regions are not covered by the plurality of word lines.

2. The non-volatile memory device of claim 1, wherein the plurality of bit lines and the plurality of word lines are sequentially formed on top of each other.

3. The non-volatile memory device of claim 1, wherein the memory elements comprise a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

4. The non-volatile memory device of claim 1, wherein the memory elements comprise an oxide-nitride-oxide (ONO) structure.

5. The non-volatile memory device of claim 1, wherein the memory elements comprise a Band-gap Engineered (BE)-SONOS structure.

6. The non-volatile memory device of claim 1, wherein the memory elements comprise a top silicon-oxide-nitride-oxide-silicon-oxide-silicon (SONOSOS) structure.

7. The non-volatile memory device of claim 1, wherein the memory elements comprise a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

8. The non-volatile memory device of claim 1, wherein the memory elements comprise a silicon nitride (SiN) structure.

9. The non-volatile memory device of claim 1, wherein the memory elements comprise a Hi-K material.

10. The non-volatile memory device of claim 9, wherein the Hi-K material is HfO₂, AlN or Al₂O₃.

11. The non-volatile memory device of claim 1, wherein the plurality of bit lines comprise a P-type semiconductor material, and wherein the source/drain regions comprise N+ regions in the P-type semiconductor material.

12. The non-volatile memory device of claim 1, wherein the plurality of word lines comprise polysilicon material.

13. A non-volatile memory device, comprising:

an insulator;

a bit line located over the insulator;

a trapping element located over the bit line;

a word line located over the trapping element;

a plurality of source/drain regions formed in the bit line; and

active regions in the bit line beneath the word line, and wherein the source/drain regions are not covered by the word line.

14. The non-volatile memory device of claim 13, wherein the trapping element comprises a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

15. The non-volatile memory device of claim 13, wherein the trapping element comprises a Band-gap Engineered (BE)-SONOS structure.

16. The non-volatile memory device of claim 13, wherein the trapping element comprises a Hi-K material.

17. The non-volatile memory device of claim 13, wherein the bit line comprises a P-type semiconductor material, and wherein the source/drain regions comprise N+ regions in the P-type semiconductor material.

18. The non-volatile memory device of claim 13, wherein the word line comprises polysilicon material.