Semiconductor device and manufacturing method thereof

• US 7,999,314 B2
• Filed: 06/19/2008
• Issued: 08/16/2011
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tsuzuki, Yukio, Asai, Makoto
• Primary Examiner(s): Cao; Phat X
• Assistant Examiner(s): VIEIRA, DIANA C
• Application Number:
  US12/213,469
• Publication Number:
  US 20090283798A1
• Time in Patent Office: 1,153 Days
• Field of Search: 257/330, 257/332, 257/288, 257/E29.201, 257/E29.257, 257/E29.26, 257/335, 257/339, 257/409, 257/487, 257/329, 257/E29.254, 257/E29.255, 257/E29.256, 257/E29.626, 257/331, 438/197, 438/237, 438/257, 438/259, 438/268, 438/270
• US Class Current: 257/335
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

Claims

1. A semiconductor device comprising:

an n-conductive type semiconductor substrate having a main side and a rear side, and including a trench type MOS transistor cell and a diode cell;

a p-conductive type layer arranged over a main side surface portion of the n-conductive type semiconductor substrate, and having an impurity concentration which decreases from the main side toward the rear side;

a main side n-conductive type region having an impurity concentration higher than an impurity concentration of the substrate, and arranged over a surface portion of the p-conductive type layer;

a rear side n-conductive type layer arranged over a rear side surface portion of the n-conductive type semiconductor substrate;

a main side p-conductive type region having an impurity concentration higher than the impurity concentration of the p-conductive type layer, and arranged in a surface portion of the p-conductive type layer;

a first trench which reaches the n-conductive type semiconductor substrate and penetrates the main side n-conductive type region and the p-conductive type layer;

a first electrode layer embedded in the first trench through an insulating film, and providing a gate electrode of the trench type MOS transistor cell;

a second electrode layer arranged over the main side of the n-conductive type semiconductor substrate, electrically coupled with the main side n-conductive type region and the p-conductive type layer, and providing both a source electrode of the trench type MOS transistor cell and an anode electrode of the diode cell;

a third electrode layer arranged over the rear side of the n-conductive type semiconductor substrate, electrically coupled with the rear side n-conductive type layer, and providing both a drain electrode of the trench type MOS transistor cell and a cathode electrode of the diode cell; and

a second trench which reaches an inside of the p-conductive type layer and does not penetrate the p-conductive type layer,

wherein the second trench penetrates the main side n-conductive type region and the main side p-conductive type region,

wherein the second electrode layer is embedded in the second trench, and the second electrode layer is electrically coupled with a first part of the p-conductive type layer at a bottom of the second trench,

wherein an impurity concentration of the first part of the p-conductive type layer is lower than an impurity concentration of a second part of the p-conductive type layer, and

wherein the second electrode layer is electrically coupled with the main side p-conductive type region at a sidewall of the second trench.

2. The semiconductor device according to claim 1,

wherein electrical connection between the second electrode layer and the main side p-conductive type region is ohmic contact.

3. The semiconductor device according to claim 2,

wherein a contact portion of the main side p-conductive type region which contacts the second electrode layer has a p-conductive type impurity concentration higher than a portion of the main side p-conductive type region other than the contact portion.

4. A manufacturing method of the semiconductor device according to claim 3 comprising:

implanting an ion on the main side of the n-conductive type semiconductor substrate with a predetermined angle so that the contact portion of the main side p-conductive type region has the impurity concentration higher than the portion of the main side p-conductive type region.

5. The semiconductor device according to claim 1,

wherein the main side p-conductive type region includes an exposed surface which is exposed at the main side of the n-conductive type semiconductor substrate and an unexposed surface which is not exposed at the main side of the n-conductive type semiconductor substrate, and

wherein the second electrode layer is electrically coupled with the unexposed surface of the main side p-conductive type region at the sidewall of the second trench, and the second electrode layer is electrically coupled with the exposed surface of the main side p-conductive type region at the main side of the n-conductive type semiconductor substrate.

6. The semiconductor device according to claim 5,

wherein the exposed surface and the unexposed surface are arranged alternately over the main side of the n-conductive type semiconductor substrate to have a rectangular planar shape.

7. The semiconductor device according to claim 1,

wherein the main side p-conductive type region is arranged to be adjacent to the main side n-conductive type region.

8. The semiconductor device according to claim 1,

wherein electrical connection between the second electrode layer and the p-conductive type layer at least at a bottom of the second trench is schottky contact.

9. The semiconductor device according to claim 8,

wherein a barrier film is arranged between the second electrode layer and the p-conductive type layer.

10. The semiconductor device according to claim 9,

wherein the barrier film is arranged between the second electrode layer and the p-conductive type layer at the bottom of the second trench, and

wherein the barrier film is not arranged between the second electrode layer and the p-conductive type layer at a sidewall of the second trench so that the second electrode layer contacts the p-conductive type layer directly.

11. A manufacturing method of the semiconductor device according to claim 10 comprising:

arranging the second trench in the n-conductive type semiconductor substrate;

arranging the barrier film at the bottom of the second trench after the arranging the second trench without arranging the barrier film at the sidewall of the second trench by sputtering; and

performing a thermal treatment under a predetermined temperature after the second electrode layer is embedded in the second trench in which the barrier film is arranged.

12. The semiconductor device according to claim 1,

wherein the second trench is arranged to penetrate the main side n-conductive type region.

13. The semiconductor device according to claim 1,

wherein the p-conductive type layer includes a first layer disposed at the main side and a second layer disposed at an inner side

wherein an impurity concentration of the first layer is higher than an impurity concentration of the second layer, and

wherein the second trench is arranged so as to reach the second layer, and the second electrode layer is electrically coupled with the second layer.

14. A manufacturing method of the semiconductor device according to claim 1 comprising:

removing a damage layer generated in vicinity of the second trench when the second trench is arranged in the p-conductive type layer.

15. A manufacturing method of the semiconductor device according to claim 14 comprising:

arranging the second trench in the n-conductive type semiconductor substrate; and

removing the damage layer generated in the vicinity of the second trench by dry etching after arranging the second trench.

16. The semiconductor device according to claim 1,

wherein a portion of the second trench reaching the inside of the p-conductive type layer is arranged to be rounded off entirely.

17. The semiconductor device according to claim 1,

wherein a corner of a portion of the second trench reaching the inside of the p-conductive type layer is arranged to be rounded off.

18. The semiconductor device according to claim 1, further comprising:

a main side second p-conductive type region arranged in a region of the main side surface portion of the n-conductive type semiconductor substrate,

wherein the region differs from the diode cell, and the p-conductive type layer is not arranged at the region,

wherein the second electrode layer is electrically coupled with the main side second p-conductive type region,

wherein the main side second p-conductive type region, the n-conductive type semiconductor substrate and the rear side n-conductive type layer provide a second diode cell, which has the second electrode layer as an anode electrode and the third electrode layer as a cathode electrode, and is arranged adjacent to the diode cell.

19. The semiconductor device according to claim 18,

wherein the semiconductor device is used for an inverter circuit, and

wherein the diode cell and the second diode cell provide a free wheel diode.

20. The semiconductor device according to claim 1,

wherein the semiconductor device is used for an inverter circuit, and

wherein the diode cell provides a free wheel diode.

21. A semiconductor device comprising:

a p-conductive type semiconductor substrate having a main side and a rear side, and including a trench type MOS transistor cell and a diode cell;

an n-conductive type layer arranged over a main side surface portion of the p-conductive type semiconductor substrate, and having an impurity concentration which decreases from the main side toward the rear side;

a main side p-conductive type region having an impurity concentration higher than an impurity concentration of the substrate, and arranged over a surface portion of the n-conductive type layer;

a main side n-conductive type region having an impurity concentration higher than the impurity concentration of the n-conductive type layer, and arranged in a surface portion of the n-conductive type layer,

a rear side p-conductive type layer arranged over a rear side surface portion of the p-conductive type semiconductor substrate;

a first trench which reaches the p-conductive type semiconductor substrate and penetrates the main side p-conductive type region and the n-conductive type layer;

a first electrode layer embedded in the first trench through an insulating film, and providing a gate electrode of the trench type MOS transistor cell;

a second electrode layer arranged over the main side of the p-conductive type semiconductor substrate, electrically coupled with the main side p-conductive type region and the n-conductive type layer, and providing both a source electrode of the trench type MOS transistor cell and an anode electrode of the diode cell;

a third electrode layer arranged over the rear side of the p-conductive type semiconductor substrate, electrically coupled with the rear side p-conductive type layer, and providing both a drain electrode of the trench type MOS transistor cell and a cathode electrode of the diode cell; and

a second trench which reaches an inside of the n-conductive type layer and does not penetrate the n-conductive type layer,

wherein the second trench penetrates the main side p-conductive type region and the main side n-conductive type region,

wherein the second electrode layer is embedded in the second trench, and the second electrode layer is electrically coupled with a first part of the n-conductive type layer at a bottom of the second trench,

wherein an impurity concentration of the first part of the n-conductive type layer is lower than an impurity concentration of a second part of the n-conductive type layer, and

wherein the second electrode layer is electrically coupled with the main side n-conductive type region at a sidewall of the second trench.

22. The semiconductor device according to claim 21,

wherein electrical connection between the second electrode layer and the main side n-conductive type region is ohmic contact.

23. The semiconductor device according to claim 22,

wherein a contact portion of the main side n-conductive type region which contacts the second electrode layer has an n-conductive type impurity concentration higher than a portion of the main side n-conductive type region other than the contact portion.

24. A manufacturing method of the semiconductor device according to claim 23 comprising:

implanting an ion on the main side of the p-conductive type semiconductor substrate with a predetermined angle so that the contact portion of the main side n-conductive type region has the impurity concentration higher than the portion of the main side n-conductive type region.

25. The semiconductor device according to claim 21,

wherein the main side n-conductive type region includes an exposed surface which is exposed at the main side of the p-conductive type semiconductor substrate and an unexposed surface which is not exposed at the main side of the p-conductive type semiconductor substrate, and

wherein the second electrode layer is electrically coupled with the unexposed surface of the main side n-conductive type region at the sidewall of the second trench, and the second electrode layer is electrically coupled with the exposed surface of the main side n-conductive type region at the main side of the p-conductive type semiconductor substrate.

26. The semiconductor device according to claim 25,

wherein the exposed surface and the unexposed surface are arranged alternately over the main side of the p-conductive type semiconductor substrate to have a rectangular planar shape.

27. The semiconductor device according to claim 21,

wherein the main side n-conductive type region is arranged to be adjacent to the main side p-conductive type region.

28. The semiconductor device according to claim 21,

wherein electrical connection between the second electrode layer and the n-conductive type layer at least at a bottom of the second trench is schottky contact.

29. The semiconductor device according to claim 28,

wherein a barrier film is arranged between the second electrode layer and the n-conductive type layer.

30. The semiconductor device according to claim 29,

wherein the barrier film is arranged between the second electrode layer and the n-conductive type layer at the bottom of the second trench, and

wherein the barrier film is not arranged between the second electrode layer and the n-conductive type layer at a sidewall of the second trench so that the second electrode layer contacts the n-conductive type layer directly.

31. A manufacturing method of the semiconductor device according to claim 30 comprising:

arranging the second trench in the p-conductive type semiconductor substrate;

arranging the barrier film at the bottom of the second trench after the arranging the second trench without arranging the barrier film at the sidewall of the second trench by sputtering; and

performing a thermal treatment under a predetermined temperature after the second electrode layer is embedded in the second trench in which the barrier film is arranged.

32. The semiconductor device according to claim 21,

wherein the second trench is arranged to penetrate the main side p-conductive type region.

33. The semiconductor device according to claim 21,

wherein the n-conductive type layer includes a first layer disposed at the main side and a second layer disposed at an inner side

wherein an impurity concentration of the first layer is higher than an impurity concentration of the second layer, and

wherein the second trench is arranged so as to reach the second layer, and the second electrode layer is electrically coupled with the second layer.

34. A manufacturing method of the semiconductor device according to claim 21 comprising:

removing a damage layer generated in vicinity of the second trench when the second trench is arranged in the n-conductive type layer.

35. A manufacturing method of the semiconductor device according to claim 34 comprising:

arranging the second trench in the p-conductive type semiconductor substrate; and

removing the damage layer generated in the vicinity of the second trench by dry etching after arranging the second trench.

36. The semiconductor device according to claim 21,

wherein a portion of the second trench reaching the inside of the n-conductive type layer is arranged to be rounded off entirely.

37. The semiconductor device according to claim 21,

wherein a corner of a portion of the second trench reaching the inside of the n-conductive type layer is arranged to be rounded off.

38. The semiconductor device according to claim 21, further comprising:

a main side second n-conductive type region arranged in a region of the main side surface portion of the p-conductive type semiconductor substrate,

wherein the region differs from the diode cell, and the n-conductive type layer is not arranged at the region,

wherein the second electrode layer is electrically coupled with the main side second n-conductive type region,

wherein the main side second n-conductive type region, the p-conductive type semiconductor substrate and the rear side p-conductive type layer provide a second diode cell, which has the second electrode layer as an anode electrode and the third electrode layer as a cathode electrode, and is arranged adjacent to the diode cell.