Semiconductor device and manufacturing method thereof

• US 7,999,393 B2
• Filed: 12/16/2008
• Issued: 08/16/2011
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kato, Tatsuya, Endo, Masato
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Jefferson; Quovaunda
• Application Number:
  US12/335,720
• Publication Number:
  US 20090194879A1
• Time in Patent Office: 973 Days
• Field of Search: 257/758, 257773-775, 257/E23.145, 257/E23.151
• US Class Current: 257/775
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout

Abstract

A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.

Claims

1. A semiconductor device comprising:

a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique;

a plurality of second interconnection layers which are provided in the insulating layer and formed in a pattern having a width and space smaller than the resolution limit; and

,

a third interconnection layer which is provided between the first interconnection layers and the second interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer,

wherein a space between the third interconnection layer and a first interconnection layer adjacent to the third interconnection layer equals the space of the first interconnection layers, and

a space between the third interconnection layer and a second interconnection layer adjacent to the third interconnection layer equals the space of the first interconnection layers.

2. The device according to claim 1, wherein letting “

F”

be the width of the first interconnection layer, the width of the third interconnection layer satisfies

2F×

n−

F(n is a natural number of not less than

     1).

3. The device according to claim 1, wherein the space equals the width of the first interconnection layer.

4. The device according to claim 1, wherein the first interconnection layers include shallow interconnections and deep interconnections which are alternately arranged.

5. The device according to claim 1, wherein the first to third interconnection layers are made of one material selected from the group consisting of copper (Cu), aluminum (Al), and ruthenium (Ru).

6. The device according to claim 1, further comprising:

a cell group having a plurality of memory cells which are connected in series; and

a first select transistor and a second select transistor which are connected in series with ends of the cell group, respectively,

wherein each of the first and second interconnection layers is a bit line and is connected to one end of a current path of the first select transistor, and

the third interconnection layer is a shunt interconnection and is connected to one end of a current path of the second select transistor.

7. A semiconductor device comprising:

a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique;

two second interconnection layers each of which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer; and

a plurality of second interconnection layers which are provided in the insulating layer and formed in a pattern having a width and space smaller than the resolution limit;

two third interconnection layers which are provided between the first interconnection layers and the second interconnection layers in the insulating layer and have a width larger than that of a first interconnection layer; and

a fourth interconnection layer which is provided between the third interconnection layers in the insulating layer and has a width not less than that of the first interconnection layer,

wherein a space between a third interconnection layer and a first interconnection layer adjacent to the third interconnection layer equals the space of the first interconnection layers,

a space between a third interconnection layer and a second interconnection layer adjacent to the third interconnection layer equals the space of the first interconnection layers, and

a space between the fourth interconnection layer and each of the third interconnection layers equals the space of the first interconnection layers.

8. The device according to claim 7, wherein letting “

F”

be the width of the first interconnection layer, the width of the third interconnection layer satisfies

2F×

n−

F(n is a natural number of not less than

     1).

9. The device according to claim 8, wherein letting “

F”

be the width of the first interconnection layer, the width of the fourth interconnection layer satisfies

2F×

m−

F(m is a natural number of not less than

     1).

10. The device according to claim 7, wherein the space equals the width of the first interconnection layer.

11. The device according to claim 7, wherein the first interconnection layers include shallow interconnections and deep interconnections which are alternately arranged.

12. The device according to claim 7, wherein the first to fourth interconnection layers are made of one material selected from the group consisting of copper (Cu), aluminum (Al), and ruthenium (Ru).

13. The device according to claim 7, further comprising:

a cell group having a plurality of memory cells which are connected in series; and

a first select transistor and a second select transistor which are connected in series with ends of the cell group, respectively,

wherein each of the first and second interconnection layers is a bit line and is connected to one end of a current path of the first select transistor, and

one of the third interconnection layers is a shunt interconnection and is connected to one end of a current path of the second select transistor.