Interference reduction device

• US 7,999,715 B2
• Filed: 03/03/2010
• Issued: 08/16/2011
• Est. Priority Date: 05/19/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaki, Ryo, Yamagishi, Toshiyuki
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US12/716,815
• Publication Number:
  US 20100295716A1
• Time in Patent Office: 531 Days
• Field of Search: 341117-120, 341/122, 341/143, 341/155
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0656 in the time domain, e.g. using intended jitter as a dither signal
• CPC Class Codes: H03M 1/0827 of electromagnetic or electrostatic field noise, e.g. preventing crosstalk by shielding or optical isolation
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

An interference reduction device includes an analog to digital converter, a serial to parallel converter, a first FIR filter, a second FIR filters, a flip-flop, a decision unit, and a selector. The analog to digital converter performs A/D conversion. The serial to parallel converter performs a session of distribution processing in which a digital signal obtained by the A/D conversion. The first FIR outputs the signal after a filter operation at the desired output frequency. The second FIR filters each perform a filter operation, also each output the generated signals at the desired output frequency. The flip-flop samples the inputted digital signal. The decision unit decides which one of the FIR filters has the smallest influence of interference of the input digital signal. The selector outputs one of the signals outputted by the FIR filters.

Claims

1. An interference reduction device comprising:

an analog to digital converter (A/D converter;

ADC) to perform A/D conversion on input analog signal at frequency twice as high as output frequency;

a serial to parallel converter (S/P converter) to repeatedly perform a session of distribution processing in which a digital signal obtained by the A/D conversion is distributed on a symbol basis to two destinations in a predetermined order;

a digital filter to receive the signal distributed at the first timing in each session of the distribution processing and to output the signal after a filter operation at the output frequency;

an interpolation filter to receive the signal other than the signal distributed at the first timing in each session of the distribution processing, to perform a filter operation, also to perform interpolation processing to thereby generate the signal distributed to the digital filter in the distribution processing, and to output the generated signal at the output frequency;

a sampling unit to sample the inputted digital signal at frequency twice as high as the output frequency;

a decision unit to decide which one of the digital filter and the interpolation filter has received smaller influence of interference of the input digital signal, on the basis of a sampling result by the sampling unit; and

a selector to output one of the signals outputted by the digital filter and the interpolation filter, on the basis of a decision result of the decision unit.

2. The interference reduction device according to claim 1, wherein

the decision unit decides that the interpolation filter has received smaller influence of interference when an output timing of the digital filter and the interpolation filter is coincident with any of the timings of a rising edge, a falling edge, or both rising and falling edges of the signal sampled by the sampling unit, and decides that the digital filter has smaller influence of interference when the output timing is different from the edge timing.

3. The interference reduction device according to claim 1, wherein

in a case where the input analog signal receives maximum interference at least one of edge timings of a rising edge, a falling edge, and both rising and falling edges of the input digital signal, and where an intensity of the interference decreases over time,

the decision unit detects any of the timings of the rising edge, the falling edge, or both rising and falling edges of the signal sampled by the sampling unit,

assigns intensity numbers to signals sampled immediately before and after the detected timing in such a manner as to assign 1 to the signal sampled immediately before the detected timing and 2 to the signal sampled immediately after the detected timing,

assigns an intensity number to each of signals subsequent to the signal assigned the intensity number 2, the intensity number incremented by 1 from the intensity number assigned to the preceding signal,

divides the signals assigned the intensity numbers into units of output intervals of the digital filter and the interpolation filter,

detects the signal having the largest intensity number for each of the output intervals, and

decides which filter has received smaller influence of interference, on the basis of the detected signal.

4. The interference reduction device according to claim 1, wherein

the digital filter and the interpolation filter are FIR filters.

5. The interference reduction device according to claim 4, wherein

the decision unit includes:

a serial to parallel converter to repeatedly perform a session of sampling signal distribution processing in which a signal sampled by the sampling unit is distributed to two destinations in a predetermined order;

two interference intensity calculation units to receive the signal distributed by the serial-to-parallel converter, and calculate interference intensities of the digital filter and the interpolation filter, respectively, on the basis of the inputted signal and tap coefficients used in the digital filter and the interpolation filter; and

a comparator to compare the interference intensities respectively calculated by the two interference intensity calculation units, and

the decision unit decides which filter has received smaller influence of interference, on the basis of a comparison result of the comparator.

6. The interference reduction device according to claim 1, wherein

the interference reduction device is installed in a communication apparatus.

7. The interference reduction device according to claim 1, wherein

the sampling unit is a flip-flop.

8. An interference reduction device comprising:

an analog to digital converter (A/D converter;

ADC) to perform A/D conversion on input analog signal at frequency M (M is an integer of 3 or more) times as high as output frequency;

a serial to parallel converter (S/P converter) to repeatedly perform a session of distribution processing in which a digital signal obtained by the A/D conversion is distributed on a symbol basis to M destinations in a predetermined order;

a digital filter to receive the signal distributed at the first timing in each session of the distribution processing and to output the signal after a filter operation at the output frequency;

(M−

1) interpolation filters each to receive the signal other than the signal distributed at the first timing in each session of the distribution processing, to perform a filter operation, also to perform interpolation processing to thereby generate the signal distributed to the digital filter in the distribution processing, and to output the generated signal at the output frequency;

a sampling unit to sample the inputted digital signal at frequency M times as high as the output frequency;

a decision unit to decide which one of the digital filter and the (M−

1) interpolation filters has the smallest influence of interference of the input digital signal, on the basis of a sampling result by the sampling unit; and

a selector to output one of the signals outputted by the digital filter and the (M−

1) interpolation filters, on the basis of a decision result of the decision unit.

9. The interference reduction device according to claim 8, wherein

in a case where the input analog signal receives maximum interference at least one of edge timings of a rising edge, a falling edge, and both rising and falling edges of the input digital signal, and where an intensity of the interference decreases over time,

the decision unit detects any of the timings of a rising edge, a falling edge, or both rising and falling edges of the signal sampled by the sampling unit,

assigns intensity numbers to signals sampled immediately before and after the detected timing in such a manner as to assign 1 to the signal sampled immediately before the detected timing and 2 to the signal sampled immediately after the detected timing,

a assigns an intensity number to each of signals subsequent to the signal assigned the intensity number 2, the intensity number incremented by 1 from the intensity number assigned to the preceding signal,

divides the signals assigned the intensity numbers into units of output intervals of the digital filter and the (M−

1) interpolation filters,

detects the signal having the largest intensity number for each of the output intervals, and

decides which filter has received smallest influence of interference, on the basis of the detected signal.

10. The interference reduction device according to claim 8, wherein

the digital filter and the (M−

1) interpolation filters are FIR filters.

11. The interference reduction device according to claim 10, wherein

the decision unit includes:

a serial to parallel converter to repeatedly perform a session of sampling signal distribution processing in which a signal sampled by the sampling unit is distributed to M destinations in a predetermined order;

M interference intensity calculation units to receive the signal distributed by the serial-to-parallel converter, and calculate interference intensities of the digital filter and the (M−

1) interpolation filters, respectively, on the basis of the inputted signal and tap coefficients used in the digital filter and the (M−

1) interpolation filters; and

a comparator to compare the interference intensities respectively calculated by the M interference intensity calculation units, and

the decision unit decides which filter has received the smallest influence of interference, on the basis of a comparison result of the comparator.

12. The interference reduction device according to claim 8, wherein

the sampling unit is a flip-flop.

13. The interference reduction device according to claim 8, wherein

the interference reduction device is installed in a communication apparatus.

14. An interference reduction device comprising:

an analog to digital converter (A/D converter;

ADC) to perform A/D conversion on input analog signal at frequency M (M is an integer of 3 or more) times as high as output frequency;

a serial to parallel converter (S/P converter) to repeatedly perform a session of distribution processing in which a digital signal obtained by the A/D conversion is distributed on a symbol basis to M destinations in a predetermined order;

a buffer to receive the signal distributed at the first timing in each session of the distribution processing and to output the symbols in a first-in first-out order;

(M−

1) interpolation filters each to receive the signal other than the signal distributed at the first timing in each session of the distribution processing, to perform a filter operation, also to perform interpolation processing to thereby generate the signal distributed to the buffer in the distribution processing, and to output the generated signal at the output frequency;

a sampling unit to sample the inputted digital signal at frequency M times as high as the output frequency;

a decision unit to decide which one of the buffer and the (M−

1) interpolation filters has received the smallest influence of interference of the input digital signal, on the basis of a sampling result by the sampling unit; and

a selector to output one of the signals outputted by the buffer and the (M−

1) interpolation filters, on the basis of a decision result of the decision unit.

15. The interference reduction device according to claim 14, wherein the buffer is a FIFO memory.

16. The interference reduction device according to claim 14, wherein

the interference reduction device is installed in a communication apparatus.