Non-volatile memory with both single and multiple level cells

• US 8,000,136 B2
• Filed: 07/19/2010
• Issued: 08/16/2011
• Est. Priority Date: 08/21/2006
• Status: Active Grant

• Current Assignee: Mirion Technologies Incorporated (American Capital Limited)
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/838,646
• Publication Number:
  US 20100277981A1
• Time in Patent Office: 393 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.

Claims

1. A memory array, comprising:

a number of strings of memory cells each including a number of memory cells coupled in series between a first select gate at a first end of the string and a second select gate at a second end of the string;

wherein for each of the strings of memory cells;

the first select gate is directly coupled to a first memory cell operated as a single level cell;

the second select gate is directly coupled to a second memory cell operated as a single level cell;

a continuous number of memory cells, interposed between and coupled to the first memory cell and the second memory cell, are operated as multiple level memory cells;

wherein the number of memory cells operated as multiple level memory cells are configured to have a lower page programming process and an upper page programming process performed thereon; and

wherein the second memory cell is configured to be programmed from an erased state subsequent to the upper page programming process.

2. The array of claim 1, wherein the number of memory cells operated as multiple level memory cells are comprised of a lower page and at least one upper page of data and the first and second memory cells operated as single level memory cells are comprised of a single page of data.

3. The array of claim 2, wherein the first memory cell operated as a single level cell has a programmed voltage that is less than a lowest programmed voltage of the at least one upper page of data of the number of memory cells operated as multiple level memory cells and that is greater than a resting voltage of the first select gate.

4. The array of claim 2, wherein the second memory cell operated as a single level cell has a programmed voltage that is less than a lowest programmed voltage of the at least one upper page of data of the number of memory cells operated as multiple level memory cells and that is greater than a resting voltage of the second select gate.

5. A memory array, comprising:

a number of strings of memory cells each including a number of memory cells coupled in series between a first select gate at a first end of the string and a second select gate at a second end of the string;

wherein for each of the strings of memory cells;

the first select gate is directly coupled to a first memory cell operated as a single level cell;

the second select gate is directly coupled to a second memory cell operated as a single level cell;

a continuous number of memory cells, interposed between and coupled to the first memory cell and the second memory cell, are operated as multiple level memory cells; and

wherein the second memory cell is programmed from an erased state subsequent to programming the continuous number of memory cells.

6. The array of claim 5, wherein a first memory cell of a second string is configured to be programmed prior to programming a continuous number of memory cells of the first and second strings.

7. The array of claim 5, wherein a continuous number of memory cells of a second string are configured to be programmed subsequent to programming the first memory cell of the first string, the continuous number of memory cells of the first string, and a first memory cell of the second string.

8. A memory array, comprising:

a number of strings of memory cells each including a number of memory cells coupled in series between a first select gate at a first end of the string and a second select gate at a second end of the string;

wherein for each of the strings of memory cells;

the first select gate is directly coupled to a first memory cell operated as a single level cell;

the second select gate is directly coupled to a second memory cell operated as a single level cell;

a continuous number of memory cells, interposed between and coupled to the first memory cell and the second memory cell, are operated as multiple level memory cells; and

wherein the second memory cell operated as a single level cell and coupled to the second end of a first string is configured to be programmed from an erased state subsequent to programming the first memory cell operated as a single level cell and coupled to the first end of the first string and subsequent to programming a lower page and an upper page for each of the continuous number of memory cells of the first string.

9. The array of claim 8, wherein the number of memory cells comprise non-volatile floating gate memory cells in at least one NAND string.

10. The array of claim 8, wherein the continuous number of memory cells comprises at least 30 memory cells that are operated as multiple level memory cells.

11. A method of operating a memory array, comprising:

programming a single page on a first memory cell located at a first end of a first string of memory cells;

programming a lower page and an upper page on each of a number of memory cells coupled in series with the first memory cell; and

programming a single page on a second memory cell that is in an erased state and is located at a second end of the first string of memory cells subsequent to programming the upper page on at least one of the number of memory cells coupled in series with the first memory cell.

12. The method of claim 11, including programming the single page on the second memory cell subsequent to programming the lower page and the upper page on each of the number of memory cells coupled in series with the first memory cell, wherein the first memory cell, the second memory cell, and the number of memory cells coupled in series with the first memory cell form a string of memory cells, and wherein only the first and second memory cells are operated as single level cells.

13. The method of claim 11, including programming the single page on the second memory cell prior to programming the upper page on at least one of the number of memory cells coupled in series with the first memory cell.

14. The method of claim 11, including programming a single page on a first memory cell located at a first end of a second string of memory cells sequentially subsequent to programming the single page on the first memory cell located at the first end of the first string of memory cells.

15. The method of claim 14, including programming a lower page and an upper page on each of a number of memory cells coupled in series with the first memory cell located at a first end of the second string of memory cells.

16. The method of claim 15, including programming a single page on a second memory cell located at a second end of the second string of memory cells subsequent to programming the lower page and the upper page on each of the number of memory cells coupled in series with the first memory cell located at the first end of the second string of memory cells.

17. The method of claim 14, including programming the lower page and the upper page on a memory cell directly coupled to the first memory cell located at the first end of the first string of memory cells sequentially subsequent to programming the single page on the first memory cell located at the first end of the second string of memory cells.

18. The method of claim 17, including programming a lower page and an upper page on a memory cell directly coupled to the first memory cell located at the first end of the second string of memory cells sequentially subsequent to programming the lower page and the upper page on the memory cell directly coupled to the first memory cell located at the first end of the first string of memory cells.

19. The method of claim 18, including programming a lower page and an upper page on a memory cell directly coupled to the first memory cell located at the first end of the second string of memory cells sequentially subsequent to programming the lower page and the upper page on the memory cell directly coupled to the first memory cell located at the first end of the first string of memory cells.

20. The method of claim 14, including programming the lower page on a memory cell directly coupled to the first memory cell located at the first end of the first string of memory cells and a lower page on a memory cell directly coupled to the first memory cell located at the first end of the second string of memory cells sequentially subsequent to programming the single page on the first memory cell located at the first end of the second string of memory cells.

21. The method of claim 20, including programming a lower page on a memory cell indirectly coupled to the first memory cell located at the first end of the first string of memory cells and a lower page on a memory cell indirectly coupled to the first memory cell located at the first end of the second string of memory cells sequentially subsequent to programming the lower pages on the memory cells directly coupled to the first memory cells located at the first ends of the first and second strings of memory cells.

22. The method of claim 21, including programming the upper page on a memory cell directly coupled to the first memory cell located at the first end of the first string of memory cells and an upper page on a memory cell directly coupled to the first memory cell located at the first end of the second string of memory cells sequentially subsequent to programming the lower pages on the memory cells indirectly coupled to the first memory cells located at the first ends of the first and second strings of memory cells.

23. The method of claim 22, including programming an upper page on the memory cell indirectly coupled to the first memory cell located at the first end of the first string of memory cells and an upper page on the memory cell indirectly coupled to the first memory cell located at the first end of the second string of memory cells sequentially subsequent to programming lower pages on memory cells indirectly coupled to the memory cells directly coupled to the first memory cells located at the first ends of the first and second strings of memory cells.

24. A method of operating a memory array, comprising:

programming a single page on a memory cell located at a first end of a first string of memory cells;

programming a single page on a memory cell located at a first end of a second string of memory cells;

subsequent to at least programming the single page on the memory cell located at the first end of the first string of memory cells, programming a plurality of pages on each of a number of memory cells coupled in series with the memory cell located at the first end of the first string of memory cells;

subsequent to at least programming the single page on the memory cell located at the first end of the second string of memory cells, programming a plurality of pages on each of a number of memory cells coupled in series with the memory cell located at the first end of the second string of memory cells; and

programming a single page on a second memory cell that is in an erased state and is located at a second end of the first string of memory cells subsequent to programming the plurality of pages on at least one of the number of memory cells coupled in series with the second memory cell.

25. The method of claim 24, including programming a single page on a second memory cell located at a second end of the second string of memory cells.

26. The method of claim 24, including programming the single page on the memory cell located at the first end of the second string of memory cells subsequent to programming the single page on the second memory cell located at the second end of the first string of memory cells.

27. The method of claim 24, including programming the single page on the memory cell located at the first end of the second string of memory cells subsequent to programming the plurality of pages on each of the number of memory cells coupled in series with the memory cell located at the first end of the first string of memory cells.

28. The method of claim 24, including programming the single page on the memory cell located at the first end of the second string of memory cells prior to programming the plurality of pages on each of the number of memory cells coupled in series with the memory cell located at the first end of the first string of memory cells.

29. The method of claim 24, including programming the single page on the memory cell located at the second end of the first string of memory subsequent to programming the plurality of pages on each of the number of memory cells coupled in series with the memory cell located at the first end of the first string of memory cells.

30. The method of claim 24, including programming the single page on the memory cell located at the second end of the first string of memory cells prior to programming the plurality of pages on each of the number of memory cells coupled in series with the memory cell located at the first end of the first string of memory cells.