Semi-volatile NAND flash memory

• US 8,000,142 B1
• Filed: 05/03/2010
• Issued: 08/16/2011
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Montierth, Mark D., Keithley, Douglas G., Briggs, Randall D.
• Primary Examiner(s): Mai; Son L
• Application Number:
  US12/772,819
• Time in Patent Office: 470 Days
• Field of Search: 365/185.09
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Claims

1. A NAND flash memory device comprising:

a NAND flash memory comprising

a first retention region comprising one or more first memory cells, the one or more first memory cells configured to store data for a first amount of time based at least in part on a number of write cycles applied to the first retention region, and

a second retention region comprising one or more second memory cells, the one or more second memory cells configured to store data for a second amount of time, the second amount of time being greater than the first amount of time; and

a memory controller configured to periodically read data from the one or more first memory cells and rewrite the read data to the same one or more first memory cells as a refresh operation,

wherein the memory controller is further configured to relocate data stored in the one or more first memory cells of the first retention region to the one or more second memory cells of the second retention region based at least in part on a refresh period between refresh operations, the refresh period being a predetermined amount of time that is based at least in part on the number of write cycles applied to the first retention region.

2. The NAND flash memory device of claim 1, wherein the NAND flash memory is semi-volatile.

3. The NAND flash memory device of claim 1, wherein the NAND flash memory is implemented on a single chip.

4. The NAND flash memory device of claim 1, wherein the memory controller is configured to perform wear-leveling on the first retention region and the second retention region.

5. The NAND flash memory device of claim 1, wherein the predetermined number of times corresponds to a fixed wear-out metric.

6. A system comprising:

a bus;

a processor in communication with the bus; and

the NAND flash memory device of claim 1,

wherein the memory controller of the NAND flash memory is in communication with the bus.

7. The system of claim 6, wherein the system comprises a CD player.

8. The system of claim 6, wherein the system comprises a printer.

9. A method comprising:

storing data in one or more first memory cells of a NAND flash memory, the one or more first memory cells being configured to store the data for a first amount of time based at least in part on a number of write cycles applied to the one or more first memory cells,

periodically performing refresh operations on the one or more first memory cells, including;

reading data from the one or more first memory cells, and

rewriting the read data to the same one or more first memory cells, and

relocating the data stored in the one or more first memory cells of the first retention region to one or more second memory cells of the NAND flash memory based at least in part on a refresh period between refresh operations, wherein the refresh period is a predetermined amount of time that is based at least in part on the number of write cycles applied to the first retention region, and

wherein the one or more second memory cells is configured to store data for a second amount of time, the second amount of time being greater than the first amount of time.

10. The method of claim 9, wherein the NAND flash memory is semi-volatile.

11. The method of claim 9, wherein the NAND flash memory is implemented on a single chip.

12. The method of claim 9, further comprising performing wear-leveling on the one or more first memory cells and the one or more second memory cells.

13. The method of claim 9, wherein the predetermined number of times corresponds to a fixed wear-out metric.