Method and system for accessing a flash memory device

• US 8,000,144 B2
• Filed: 03/26/2010
• Issued: 08/16/2011
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/732,745
• Publication Number:
  US 20100182838A1
• Time in Patent Office: 508 Days
• Field of Search: 365/221
• US Class Current: 365/185.11
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A method of addressing at least one memory block in a flash memory device, comprising:

receiving a data stream at any one of a plurality of interfaces;

determining a flash memory block associated with the data stream; and

addressing the flash memory block from the any one of the plurality of interfaces.

2. The method of claim 1, wherein determining the flash memory block associated with the data stream comprises decoding command data in the data stream to determine the flash memory block associated with the data stream.

3. The method of claim 1, wherein receiving the data stream comprises receiving single-bit-wide data streams at any one of the plurality of interfaces.

4. The method of claim 1, wherein decoding command data in the data stream comprises analyzing the data stream to determine a command word and at least one of a column, row or bank address word.

5. The method of claim 1, further comprising:

receiving a further data stream at another of the plurality of interfaces;

decoding command data in the further data stream to determine a second flash memory block associated with the further data stream; and

addressing the second flash memory block while concurrently addressing the flash memory bank.

6. The method of claim 1, further comprising transferring data to or from the flash memory block.

7. A flash memory device having at least one memory bank comprising:

a plurality of data link interfaces, each configured for receiving a data stream containing access data; and

a control module for determining a selected memory bank of the at least one memory bank associated with the data stream in response to information in the access data, and transfer data between any one of the plurality of data link interfaces and the selected memory bank.

8. The device of claim 7, wherein each of the plurality of data link interfaces is configured for outputting one of the data stream and read data.

9. The device of claim 7, wherein the data stream is a single-bit-wide data stream.

10. The device of claim 9, wherein the access data includes a command, an address, and a memory bank identifier, the control module determining the selected memory bank in response to the memory bank identifier.

11. The device of claim 10, wherein each of the plurality of data link interfaces includes a command interpreter for decoding the command.

12. The device of claim 10, wherein each of the plurality of data link interfaces is configured for outputting read data from the selected memory bank in response to the command and the address, when the command corresponds to a read operation.

13. The device of claim 12, wherein output data provided from the selected memory bank is provided in parallel, and each of the plurality of data link interfaces includes a parallel to serial circuit for converting the output data into the read data in a single-bit-wide data stream.

14. The device of claim 9, wherein each of the plurality of data link interfaces includes a serial to parallel circuit for converting the single-bit-wide data stream into parallel data.

15. The device of claim 7, wherein the control module includes a switch circuit for coupling one of the plurality of data link interfaces with the selected memory bank.

16. The device of claim 15, wherein the switch circuit couples command information and address information of the access data received at any one of the plurality of data link interfaces to one of the selected memory bank and another memory bank.

17. The device of claim 16, wherein the switch circuit couples the command information and the address information as parallel bits of data.

18. The device of claim 16, wherein the switch circuit is controllable for coupling output data from one of the selected memory bank and another memory bank to any one of the plurality of data link interfaces.

19. The device of claim 16, wherein the access data includes program data, and the switch circuit is controllable for coupling the program data from any one of the plurality of data link interfaces to one of the selected memory bank and another memory bank.