Method of metal pattern inspection verification

• US 8,000,519 B1
• Filed: 04/04/2007
• Issued: 08/16/2011
• Est. Priority Date: 04/04/2007
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Zheng, Yongjun, Mark, David, Zhao, Joe W., Pagaduan, Felino Encarnacion
• Primary Examiner(s): Bella; Matthew
• Assistant Examiner(s): Rush; Eric
• Application Number:
  US11/732,859
• Time in Patent Office: 1,595 Days
• Field of Search: 382/141, 382145-151, 382/100, 438/10, 438/14, 438/16, 438/17, 324/71.5, 324/500, 324/512, 324/522, 324/523, 324/527, 324/528, 324/531, 324/537, 702 81- 84
• US Class Current: 382/145
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14

Abstract

A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M6), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.

Claims

1. A method of evaluating an inline inspection recipe comprising:

setting up a first inline inspection process of a patterned metal layer on a wafer according to first inline inspection parameters;

inspecting the patterned metal layer to capture metal pattern defect data;

processing the wafer to produce integrated circuits for electrical test, each of the integrated circuits being essentially identical;

applying a test vector to the integrated circuits to capture electrical failures for a plurality of failed integrated circuits;

calculating a bounding box for the plurality of failed integrated circuits in accordance with the test vector;

mapping metal pattern defect data for each of the plurality of failed integrated circuits to the bounding box;

calculating a first capture rate;

wherein the first capture rate is calculated as a function of a total number of those of the failed integrated circuits for which the metal pattern defect data maps to the bounding box, and of a total number of the failed integrated circuits;

shifting the bounding box for each of the plurality of failed integrated circuits to provide an offset bounding box for each of the plurality of failed integrated circuits;

mapping metal pattern defect data to the offset bounding box for each of the plurality of failed integrated circuits;

calculating a second capture rate;

wherein the second capture rate is calculated as a function of a total number of those of the failed integrated circuits for which the metal pattern defect data maps to the offset bounding box, and a total number of the failed integrated circuits;

comparing the first capture rate to the second capture rate to produce a difference; and

adjusting the inline inspection recipe according to the difference to improve capture of killer defects.

2. The method of claim 1 further comprising applying a second test vector to the integrated circuits and calculating a second bounding box for the integrated circuits in accordance with the second test vector.

3. The method of claim 1 wherein the bounding box has a dimension that is parallel to an edge of an integrated circuit of the integrated circuits, and

wherein the shifting the bounding boxes comprises shifting the bounding box in a direction that is parallel to the edge by at least the dimension.

4. The method of claim 1 wherein the integrated circuits are field-programmable gate arrays (“

FPGAs”

), and the bounding box extends from a first edge of an FPGA to an opposite edge of the FPGA.

5. The method of claim 4 wherein the bounding box has a dimension along the first edge, and the dimension is equivalent to not more than five configurable logic blocks of the FPGA.

6. The method of claim 5 wherein the shifting the bounding box comprises shifting the bounding box at least the dimension in a direction parallel to the first edge to produce the offset bounding box, and

wherein, if the second capture rate is greater than one half the first capture rate, the inline inspection recipe is adjusted, and if the second capture rate is less than or equal to one half the first capture rate, the inline inspection recipe is not adjusted.

7. The method of claim 5 wherein the shifting the bounding box comprises shifting the bounding box at least the dimension in a direction parallel to the first edge to produce the offset bounding box, and

wherein, if the second capture rate is less than or equal to 10%, the inline inspection recipe is not adjusted.

8. The method of claim 7 wherein the first capture rate is greater than 40%.

9. The method of claim 5 wherein the dimension is equivalent to three configurable logic blocks of the FPGA.

10. The method of claim 1 wherein the integrated circuits are field-programmable gate arrays (“

FPGAs”

) and the test vector is routed through a selected patterned metal layer of the FPGAs.

11. The method of claim 10 wherein the FPGAs have at least six patterned metal layers and the selected patterned metal layer is above a fifth patterned metal layer.

12. The method of claim 1 wherein, if the second capture rate is greater than one half the first capture rate, the inline inspection recipe is adjusted, and if the second capture rate is less than or equal to one half the first capture rate, the inline inspection recipe is not adjusted.

13. The method of claim 1 wherein, if the difference is at least one half of the first capture rate the inline inspection recipe is not adjusted and if the difference is less than one half of the first capture rate the inline inspection recipe is adjusted.

14. The method of claim 1 wherein the inline inspection recipe is not adjusted if the second capture rate is less than 10%.

15. A method of evaluating an inline inspection recipe comprising:

inspecting a patterned metal layer of partially fabricated integrated circuits (ICs) on a wafer according to a first set of inspection parameters to capture metal pattern defect data;

processing the wafer to produce a plurality of ICs from the partially fabricated ICs;

designing a test vector to capture electrical failures in the patterned metal layer;

applying the test vector to the plurality of ICs to detect an electrical failure on the plurality of ICs;

calculating a bounding box on the plurality of ICs according to the test vector, the electrical failure being within the bounding box;

mapping the metal pattern defect data for the metal layer to the bounding box;

calculating a first capture rate;

wherein the first capture rate is calculated as a function of a total number of the plurality of ICs for which the metal pattern defect data maps to the bounding box, and a total number of the plurality of ICs in which the electrical failure was detected;

shifting the bounding box to define a shifted bounding box on the IC;

mapping metal pattern defect data for the metal layer to the shifted bounding box;

calculating a second capture rate;

wherein the second capture rate is calculated as a function of a total number of the plurality of ICs for which the metal pattern defect data maps to the shifted bounding box, and a total number of the plurality of ICs in which the electrical failure was detected; and

comparing the first capture rate to the second capture rate.

16. The method of claim 15 wherein the patterned metal layer is above a fifth patterned metal layer of the IC.

17. The method of claim 15 wherein the bounding box extends from a first edge of each of the plurality of ICs to a second edge of each of the plurality of ICs opposite the first edge along a first axis, and wherein the bounding box has a dimension along a second axis perpendicular to the first axis, the dimension spanning not more than five configurable logic blocks of each of the plurality of ICs.

18. The method of claim 15 further comprising,

designing a second test vector to capture electrical failures in the patterned metal layer;

applying the second test vector to the plurality of ICs to detect a second electrical failure;

calculating a second bounding box on the plurality of ICs according to the second test vector, the second electrical failure being within the second bounding box;

mapping metal pattern defect data for the metal layer to the second bounding box;

calculating a third capture rate;

wherein the third capture rate is calculated as a function of a total number of the plurality of ICs for which the metal pattern defect data maps to the second bounding box, and a total number of the plurality of ICs in which the second electrical failure was detected;

shifting the second bounding box to define a second shifted bounding box on the plurality of ICs;

mapping metal pattern defect data for the metal layer to the second shifted bounding box;

calculating a fourth capture rate;

wherein the fourth capture rate is calculated as a function of a total number of the plurality of ICs for which the metal pattern defect data maps to the second shifted bounding box, and a total number of the plurality of ICs in which the second electrical failure was detected; and

comparing the third capture rate to the fourth capture rate.

19. The method of claim 18 wherein the second shifted bounding box partially overlaps the second bounding box.