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Predicting IC manufacturing yield by considering both systematic and random intra-die process variations

  • US 8,000,826 B2
  • Filed: 01/24/2006
  • Issued: 08/16/2011
  • Est. Priority Date: 01/24/2006
  • Status: Active Grant
First Claim
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1. A method for predicting a manufacturing yield for a die within a semiconductor wafer, the method comprising:

  • receiving a physical layout of the die;

    partitioning the die into an array of tiles;

    computing systematic variations for a quality indicative parameter across the array of tiles based on the physical layout of the die, which includes;

    performing a physical layout extraction across the array of tiles; and

    determining values for the quality indicative parameter based at least on results of the physical layout extraction;

    applying a random variation for the quality indicative parameter to each tile in the array of tiles;

    iteratively placing instances of a window in the die until the die is covered with instances of the window, wherein each iteration includes,selecting a tile from the array of tiles which satisfies a criterion and is not covered by an instance of the window, andplacing an instance of the window around the selected tile;

    computing spatial correlations for the random variations between the selected tiles; and

    computing the manufacturing yield for the die based at least on the systematic variations, the random variations, and the spatial correlations for the random variations.

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