High speed filter
First Claim
1. A circuit for correlating an input signal comprising:
- a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produce a scaled signal,wherein the scaling factors in successive processing elements correspond to the coefficients in a Fourier series approximation of a desired frequency response;
a timing circuit for causing the scaled signal to be presented in time-delayed succession to be successive sampled by the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample,wherein the timing circuit is configured to cause the timing signal to be presented in time-delayed succession to successive ones of said analog sampling unit processing elements, said timing circuit comprising a timing element in parallel with an associated analog sampling unit processing element, and said timing element comprising a phase lock loop or a delay lock loop; and
a multiplier configured to multiply the scaled signal and produce an outputwherein the multiplier includes each analog sample unit processing element to scale the output and sum the scaled outputs of said processing elements.
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Accused Products
Abstract
An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.
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Citations
13 Claims
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1. A circuit for correlating an input signal comprising:
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a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produce a scaled signal, wherein the scaling factors in successive processing elements correspond to the coefficients in a Fourier series approximation of a desired frequency response; a timing circuit for causing the scaled signal to be presented in time-delayed succession to be successive sampled by the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample, wherein the timing circuit is configured to cause the timing signal to be presented in time-delayed succession to successive ones of said analog sampling unit processing elements, said timing circuit comprising a timing element in parallel with an associated analog sampling unit processing element, and said timing element comprising a phase lock loop or a delay lock loop; and a multiplier configured to multiply the scaled signal and produce an output wherein the multiplier includes each analog sample unit processing element to scale the output and sum the scaled outputs of said processing elements. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit for correlating an input signal comprising:
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a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produce a scaled signal, wherein the scaling factors in successive processing elements correspond to coefficients in a Fourier series approximation of a desired frequency response, and said circuit for scaling comprises a multiplier having as inputs the output of said sampling circuit and a predetermined scaling factor, the outputs of said multipliers being summed, a timing circuit for causing the scaled signal to be presented in time-delayed succession to be successive sampled by the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample, wherein the timing circuit is configured to cause the timing signal to be presented in time-delayed succession to successive ones of said analog sampling unit processing elements, said timing circuit comprising a timing element in parallel with an associated analog sampling unit processing element, and said timing element comprising a phase lock loop or a delay lock loop said timing circuit comprises a plurality of delay elements, the outputs of which are presented to successive ones of said processing elements; and a multiplier configured to multiply the scaled signal and produce an output, wherein the multiplier includes each analog sample unit processing element to scale the output and sum the scaled outputs of said processing elements. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification