Method and apparatus for reducing host processor activity during interaction with peripheral devices

• US 8,001,285 B1
• Filed: 12/08/2008
• Issued: 08/16/2011
• Est. Priority Date: 12/11/2007
• Status: Active Grant

• Current Assignee: Marvell Israel Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell Israel Limited (Marvell Technology Group Limited)
• Inventors: Bar-Shalom, Ofer
• Primary Examiner(s): Tsai; Henry W
• Assistant Examiner(s): Borromeo; Juanito C
• Application Number:
  US12/330,217
• Time in Patent Office: 981 Days
• Field of Search: 710/5, 712/400
• US Class Current: 710/5
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A system includes first memory for storing data and a processing core for executing software instructions on the data that is received from the first memory. The system also includes a peripheral device configured to communicate with the processing core through a peripheral control module. The peripheral control module, also referred to as a peripheral control device, includes second memory. The peripheral control module also includes a comparator for governing data transfer transactions, without interrupting the processing core, based on a comparison. The comparator therefore compares expected responses to command sequences and received responses to the command sequences. The command sequences and responses to command sequences are associated with data packets to be exchanged between the first memory and the peripheral device.

Claims

1. A system, comprising:

first memory for storing data;

a processing core for executing software instructions on the data that is received from the first memory;

a peripheral device configured to communicate with the processing core through a peripheral control module; and

the peripheral control module includes;

second memory;

an interface module configured to transmit command sequences to the peripheral device; and

a comparator for governing data transfer transactions, without interrupting the processing core, based on a comparison of expected responses of the peripheral device to received responses from the peripheral device,

wherein the received responses are generated based on the command sequences,

wherein the expected responses are predetermined based on the command sequences,

wherein the command sequences are associated with data packets to be exchanged between the first memory and the peripheral device,

wherein each of the expected responses and each of the received responses is associated with a respective command of the command sequences, and

wherein the processing core is in a sleep mode while the command sequences are transmitted to the peripheral device.

2. The system of claim 1, wherein the peripheral control module comprises a control register that controls transmission of the command sequences to the peripheral device when the processing core is not communicating with the peripheral device.

3. The system of claim 2, wherein the second memory includes:

a transmission command sequence buffer; and

a receive command sequence buffer,

wherein the control register, which is separate from the second memory, selectively provides the command sequences to the peripheral device from one of the transmission command sequence buffer and the receive command sequence buffer.

4. The system of claim 2, wherein the second memory includes:

a transmission response buffer; and

a receive response buffer,

wherein the control register selectively provides one of the expected responses to the comparator from one of the transmission response buffer and the receive response buffer.

5. The system of claim 2, further comprising a first direct memory access (DMA) control module that controls transfers of the command sequences and expected responses from the first memory to the peripheral control module.

6. The system of claim 5, wherein the peripheral control module includes a second DMA control module that provides payload data associated with the packets to at least one of the processing core and the peripheral device.

7. The system of claim 5, wherein the first DMA control module provides the software instructions without interruption of non-memory processes of the processing core.

8. The system of claim 2, wherein the peripheral device comprises at least one of a secure digital (SD) card, a SD input/output (SDIO) card, and a multi-media control (MMC) card.

9. The system of claim 8, wherein the SDIO card comprises a radio frequency (RF) transceiver module and an antenna that communicates with the RF transceiver module, wherein the RF transceiver module is compliant with at least one of IEEE standards 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.15.4, 802.16, 802.20, wireless media (WiMedia), ultra wide-band (UWB), global positioning system (GPS) devices and Bluetooth.

10. The system of claim 1, wherein the comparator is constructed in hardware.

11. The system of claim 1, further comprising hardware based pointers that cycle through the second memory.

12. The system of claim 1, wherein:

the processing core transmits the expected responses to the peripheral control module;

the expected responses are stored in the second memory prior to the command sequences being transmitted to the peripheral device; and

the peripheral control module compares the expected responses to the received responses without interrupting the processing core.

13. The system of claim 1, wherein the data transfer transactions are between the peripheral control module and the peripheral device.

14. The system of claim 1, wherein the expected responses and received responses are control data responses and the comparator determines if control data of the received responses matches control data of the expected responses.