Vehicle computer system with audio entertainment system

• US 8,001,290 B2
• Filed: 09/05/2008
• Issued: 08/16/2011
• Est. Priority Date: 01/07/1998
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Moeller, Mark M., Beckert, Richard D., Li, Hang
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): SUN, SCOTT C
• Application Number:
  US12/205,386
• Publication Number:
  US 20090228615A1
• Time in Patent Office: 1,075 Days
• Field of Search: None
• US Class Current: 710/15
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: B60R 2016/0322 Temporary code for documents to be reclassified to G08C, H04L or H04Q

Abstract

A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer. The computer system provides an audio manager API (application program interface) to enable applications running on the computer to control the various audio sources without knowing the hardware and implementation details of the underlying sound system. Different audio devices and their drivers control different functionality of the audio system, such as equalization, volume controls and surround sound decoding. The audio manager API transfers calls made by the applications to the appropriate device driver(s). The computer system also supports a speech recognition system. Speech utterances are picked up by a microphone and sampled at an internal sampling rate. However, the speech recognition system employs a lower sampling rate. The computer system converts microphone data from the higher internal sampling rate to the desired sampling rate by piggybacking the microphone data on command/message streams to an SPI (serial peripheral interface) of the audio DSP. The DSP performs normal low-pass filtering and down sampling on the data stream and then uses the SPI to send out the microphone data at the lower sampling rate.

Claims

1. A vehicle computer system comprising:

a central computer coupled to a vehicle component;

speakers coupled to the central computer;

an AM/FM tuner module;

one or more peripheral audio sources;

an audio manager application program interface (API) to transfer calls from an application running on the central computer to device drivers for the AM/FM tuner module and/or the one or more peripheral audio sources;

a data memory including one or more ping/pong buffers;

an audio signal processor; and

a logic unit configured to receive audio data from the AM/FM tuner module and one or more peripheral audio sources, the logic unit including a plurality of audio source direct memory access (DMA) circuits each associated with a particular storage area of an I/O memory, wherein one of the audio source DMA circuits is associated with the AM/FM tuner module and other of the audio source DMA circuits are each respectively associated with a specific one of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the audio signal processor,

wherein each audio source DMA circuit is configured to write audio data to a ping buffer within the respective particular storage area of the I/O memory, while the at least one data processor DMA circuit reads audio data from a pong buffer within a data memory.

2. A vehicle computer system as recited in claim 1, wherein the at least one data processor DMA circuit transfers the audio data read from the pong buffer to the audio signal processor for concurrent sound processing and output to the speakers, wherein the sound processing comprises at least one of sound equalization, digital crossover, bass, treble, volume, surround sound, AC-3, or Moving Pictures Experts Group (MPEG) decoding.

3. A vehicle computer system as recited in claim 1, further comprising a synchronization circuit to synchronize a first rate at which each audio source DMA circuit writes the audio data to the ping buffer with a second rate at which the at least one data processor DMA circuit reads the audio data from the pong buffer, the synchronization based at least in part on interrupts generated in the DMA circuit when a DMA process crosses a ping boundary or a pong boundary.

4. A vehicle computer system as recited in claim 1, further comprising a master clock adjuster circuit configured to monitor a first rate corresponding to a time between block data transfers of audio data from each audio source DMA circuit to the ping buffer and configured to employ read-done interrupts and a write-notification interrupt to adjust a reference audio clock associated with the at least one data processor DMA circuit reading previously written audio data from the pong buffer at a second rate such that the second rate is equal to the first rate.

5. A vehicle computer system as recited in claim 1, wherein the one or more peripheral audio sources include one or more of:

a security system;

a navigation system;

a CD-ROM changer;

or

a television tuner.

9. A vehicle computer system as recited in claim 1, wherein the audio manager API comprises an audio source control API configured to control background audio sources and a wave-out API configured to control foreground audio sources.

6. A vehicle computer system comprising:

a data memory including one or more ping/pong buffers;

a digital signal processor; and

a logic unit configured to receive audio data from one or more peripheral audio sources, the logic unit including one or more audio source direct memory access (DMA) circuits associated with specific ones of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the digital signal processor,

wherein each audio source DMA circuit is configured to;

write audio data to a ping buffer within the data memory;

wherein the at least one data processor DMA circuit is configured to;

read audio data written by two or more audio source DMA circuits from a pong buffer within the data memory and transfer the audio data written by the two or more audio source DMA circuits to the digital signal processor for concurrent processing; and

wherein audio data written by a first audio source DMA circuit to a ping gong buffer is output to a first set of speakers and audio data written by a second audio source DMA circuit to the ping gong buffer is simultaneously output to a second set of speakers.

7. A vehicle computer system as recited in claim 6, wherein the audio source DMA circuits are configured to write audio data to the ping buffer while the data processor DMA circuit reads previously written audio data from the pong buffer.

8. A vehicle computer system as recited in claim 6, wherein the one or more peripheral audio sources include one or more of:

a security system;

a navigation system;

a CD-ROM changer;

or

a television tuner.

10. A vehicle computer system as recited in claim 6, wherein the first audio source output to the first set of speakers is a foreground audio source and the second audio source output simultaneously to the second set of speakers is a background audio source.

11. A vehicle computer system as recited in claim 10, wherein the foreground audio source is one of a computer file or a text-to-speech output and the background audio source is one of an AM/FM tuner, a television tuner, a CD player, or a CD-ROM changer.

12. A vehicle computer system as recited in claim 6, further comprising:

a synchronization circuit to synchronize a first rate at which each audio source DMA circuit writes the audio data to the ping buffer with a second rate at which the at least one data processor DMA circuit reads the audio data from the pong buffer; and

a master clock adjuster circuit configured to monitor a first rate at which each audio source DMA circuit writes audio data to the ping buffer and adjust a reference audio clock associated with the at least one data processor DMA circuit reading previously written audio data from the pong buffer at a second rate such that the second rate is equal to the first rate.