Method and software for partitioned group element selection operation

• US 8,001,360 B2
• Filed: 01/16/2004
• Issued: 08/16/2011
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Kindred; Alford W
• Assistant Examiner(s): Moll; Jesse R
• Application Number:
  US10/757,925
• Publication Number:
  US 20040153632A1
• Time in Patent Office: 2,769 Days
• Field of Search: 712/223, 712/221, 712/222, 708/620, 708/523, 708/524
• US Class Current: 712/30
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/323 : for indirect branch instructions
• CPC Class Codes: G06F 9/3816 : Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Claims

1. A method of processing data in a single programmable processor, the method comprising:

decoding a single instruction for selectively arranging data, specifying a data selection operand and a first and a second register each having a register width, the single instruction independently specifying the first register and the second register, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting any one of the plurality of data elements and each field having a value not restricted by the other fields included in the data selection operand; and

providing in parallel the data elements selected by the fields to respective predetermined positions in a catenated result, wherein the predetermined positions are in the same order as the fields of the data selection operand.

2. The method of claim 1 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

3. The method of claim 2 wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2ⁿ data elements.

4. The method of claim 1 wherein the data selection operand is provided by a register specified by the single instruction.

5. The method of claim 4 wherein the data selection operand has a width equal to the specified register width.

6. The method of claim 1 wherein the catenated result is provided to a register.

7. The method of claim 1 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

8. The method of claim 1 wherein the instruction further specifies a data element width of the plurality of data elements.

9. The method of claim 1 wherein each data element has a width of 8 bits.

10. The method of claim 1 wherein the catenated result has a width of 128 bits.

11. The method of claim 1 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

12. The method of claim 1 further comprising:

decoding a second single instruction specifying a third and a fourth register each containing a plurality of floating-point operands;

multiplying the plurality of floating point operands in the third register by the plurality of floating-point operands in the fourth register to produce a plurality of products; and

providing the plurality of products to partitioned fields of a result register as a catenated result.

13. A computer-readable storage medium:

having instructions that instruct a computer system to perform operations,

at least some of the instructions including a group element selection instruction for selectively arranging data in a single programmable processor, the group element selection instruction capable of instructing a computer to perform operations comprising;

decoding the group element selection instruction specifying a data selection operand and a first and a second register each having a register width, the group element selection instruction independently specifying the first register and the second register, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting any one of the plurality of data elements and each field having a value not restricted by the other fields included in the data selection operand; and

providing in parallel the data elements selected by the fields to respective predetermined positions in a catenated result, wherein the predetermined positions are in the same order as the fields of the data selection operand.

14. The computer-readable storage medium of claim 13 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

15. The computer-readable storage medium of claim 14 wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2ⁿ data elements.

16. The computer-readable storage medium of claim 13 wherein the data selection operand is provided by a register specified by the single instruction.

17. The computer-readable storage medium of claim 16 wherein the data selection operand has a width equal to the specified register width.

18. The computer-readable storage medium of claim 13 wherein the catenated result is provided to a register.

19. The computer-readable storage medium of claim 13 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

20. The computer-readable storage medium of claim 13 wherein the instruction further specifies a data element width of the plurality of data elements.

21. The computer-readable storage medium of claim 13 wherein each data element has a width of 8 bits.

22. The computer-readable storage medium of claim 13 wherein the catenated result has a width of 128 bits.

23. The computer-readable storage medium of claim 13 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

24. The computer-readable storage medium of claim 13 wherein at least some of the instructions further include a group floating point multiply instruction for multiplying floating point data in a programmable processor, the group floating point multiply instruction capable of instructing the computer to perform operations comprising:

decoding the group floating point multiply instruction specifying a third and a fourth register each containing a plurality of floating-point operands;

multiplying the plurality of floating point operands in the third register by the plurality of floating-point operands in the fourth register to produce a plurality of products; and

providing the plurality of products to partitioned fields of a result register as a catenated result.

25. A method of processing data in a single programmable processor, the method comprising:

decoding a single instruction specifying a plurality of registers each having a register width, the plurality of registers independently specified by the single instruction and storing a plurality of data elements each having an elemental width smaller than the register width, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;

wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the plurality of data elements stored in the plurality of registers, allowing the index to select any data element from the plurality of data elements stored in the plurality of registers;

wherein each index in the index vector has a value not restricted by the other indices in the index vector; and

providing in parallel the data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register.

26. The method set forth in claim 25 wherein the plurality of registers comprises two registers.

27. The method set forth in claim 25 wherein the number of indices stored in the index register is equal to the number of predetermined positions in the destination register.

28. The method set forth in claim 25 wherein the index vector comprises n equal-sized indices and the destination register comprises n equal-sized predetermined positions.

29. The method set forth in claim 28 wherein the index stored in a lowest order set of bits of the index register provides a data element to a lowest order set of bits of the destination register, the index in a second lowest order set of bits of the index register provide a data element to a second lowest order set of bits of the destination register and the index stored in a highest order set of bits of the index register provides a data element to a highest order set of bits of the destination register.

30. The method set forth in claim 25 wherein the destination register is a 128-bit register.

31. A method of processing data in a single programmable processor, the method comprising:

decoding a single instruction specifying a first register storing a first plurality of data elements, a second register storing a second plurality of data elements, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;

wherein the single instruction independently specifies the first register and the second register;

wherein each of the first and second registers has a register width, and each of the first and second plurality of data elements has an elemental width smaller than the register width;

wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the first and second pluralities of data elements stored in the first and second pluralities of registers, allowing the index to select any data element from the first and second pluralities of data elements stored in the first and second pluralities of registers;

wherein each index in the index vector has a value not restricted by the other indices in the index vector; and

providing in parallel data elements from the first and second pluralities of data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register,

wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register.

32. The method set forth in claim 31 wherein the destination register is a 128-bit register.

33. A computer-readable storage medium having stored therein a plurality of instructions that cause a single computer processor having registers to perform operations on data elements stored in registers within the processor, the plurality of instructions comprising:

an instruction specifying a plurality of registers each having a register width, the plurality of registers independently specified by the instruction and storing a plurality of data elements each having an elemental width smaller than the register width, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;

wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the plurality of data elements stored in the plurality of registers, allowing the index to select any data element from the plurality of data elements stored in the plurality of registers;

wherein each index in the index vector has a value not restricted by the other indices in the index vector; and

wherein the instruction causes the computer processor to provide in parallel the data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register.

34. The computer-readable storage medium set forth in claim 33 wherein the plurality of registers comprises two registers.

35. The computer-readable storage medium set forth in claim 33 wherein the plurality of registers comprises two 64-bit registers storing a combined total of sixteen 8-bit data elements.

36. The computer-readable storage medium set forth in claim 33 wherein the number of indices stored in the index register is equal to the number of predetermined positions in the destination register.

37. The computer-readable storage medium set forth in claim 33 wherein the index vector comprises n equal-sized indices and the destination register comprises n equal-sized predetermined positions.

38. The computer-readable storage medium set forth in claim 37 wherein the index stored in a lowest order set of bits of the index register provides a data element to a lowest order set of bits of the destination register, the index in a second lowest order set of bits of the index register provide a data element to a second lowest order set of bits of the destination register and the index stored in a highest order set of bits of the index register provides a data element to a highest order set of bits of the destination register.

39. The computer-readable storage medium set forth in claim 33 wherein the destination register is a 128-bit register.

40. A computer-readable medium storage having stored therein a plurality of instructions that cause a single computer processor having registers to perform operations on data elements stored in registers within the processor, the plurality of instructions comprising:

an instruction specifying a first register storing a first plurality of data elements, a second register storing a second plurality of data elements, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;

wherein the instruction independently specifies the first register and the second register;

wherein each of the first and second registers has a register width, and each of the first and second plurality of data elements has an elemental width smaller than the register width;

wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the first and second pluralities of data elements stored in the first and second pluralities of registers, allowing the index to select any data element from the first and second pluralities of data elements stored in the first and second pluralities of registers;

wherein each index in the index vector has a value not restricted by the other indices in the index vector; and

wherein the instruction causes the computer processor to provide in parallel data elements from the first and second pluralities of data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register,

wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register.

41. The computer-readable storage medium set forth in claim 40 wherein the destination register is a 128-bit register.