Method and system for implementing context simulation

• US 8,001,512 B1
• Filed: 06/26/2007
• Issued: 08/16/2011
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: White, David
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/768,851
• Time in Patent Office: 1,512 Days
• Field of Search: 716/55, 716/101, 716/104, 716/119
• US Class Current: 716/119
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method, system, and computer program product are disclosed for using pattern-dependent models at early stages of the design process. This addresses the key disadvantage of prior approaches which are restricted to using such models later in the design process for IC designs that are nearly complete. Pattern-dependent manufacturing effects are extracted from early stage designs and using the extracted pattern-dependent effects to efficiently and effectively design the integrated circuit. One or more contexts are built around one or more units of the design, with examples of units being a block or cell. The units are then used in the context to generate pattern-dependent data as a basis for one or more pattern-dependent models.

Claims

1. A computer implemented method for implementing an integrated circuit design, comprising:

using at least one processor that is programmed for performing a process, the process comprising;

identifying one or more models that respectively characterize a variation in one or more characteristics of an integrated circuit block feature at each of a plurality of locations, wherein

the variation results from first interactions between a fabrication process and the integrated circuit block feature that is placed at each of the plurality of locations for identification of the one or more models in a portion of the integrated circuit design;

identifying a context or environment for the integrated circuit block feature at each of the plurality of locations or a second plurality of locations;

simulating second interactions between the integrated circuit block feature and the context or environment at the each of the plurality of locations or the second plurality of locations at which the integrated circuit block feature is placed for performing the act of simulating the second interactions; and

at the each of the plurality of locations or the second plurality of locations, performing a prediction to predict a finished product of the integrated circuit design or an electronic design based at least in part upon a result of the act of simulating the second interactions.

2. The method of claim 1 in which the portion of the design comprises a cell, macro or block of a design.

3. The method of claim 2 further comprising scoring, ranking or recommending characterized IP, cells or blocks.

4. The method of claim 1 in which the one or more models characterizes variation resulting from any one of the following processes:

the chemical mechanical polishing or CMP process, the etch process, the lithography process, deposition process or dopant implant process.

5. The method of claim 1 in which the one or more contexts or environments comprises a second set of patterns or shapes.

6. The method of claim 5 in which where the second set of patterns or shapes represent a second integrated circuit design.

7. The method of claim 6 in which the representation is in the form of another IC layout or in the form of pattern combinations from multiple layouts.

8. The method of claim 1 in which the results of simulating the interactions are used to determine placement of the portion within an actual layout, determine shape or location of wires during routing, determine shape and location of dummy fill within the integrated circuit design, generate one or more design rules, predict or assess yield associated with any design that contains the portion, generate layout patterns for pattern based hotspot matching, create or modify an OPC strategy, generate distribution of variation data based at least in part on one or more contexts or environments, simulate an electrical impact of the variation, compute statistical timing values, create or modify corner cases for RC extraction, compute resistance or capacitance for any part of the portion, evaluate sensitivity of the portion to the environment, modify any part of the layout contained in the portion, reduce the sensitivity of the portion or any part of the layout within the portion to the context or environment, evaluate one or more levels of a design, create dummy fill shapes and patterns, evaluate the electrical impact of the context or environment on the portion including analysis of timing, power, or signal integrity, select embedded third-party IP, evaluate the embedded third-party IP, perform physical verification as part of a design process, creating routing of a design or as part of post-route optimization of the design, or to assess a portion of the design during any stage of an electronic design process.

9. The method of claim 1 further comprising:

creating or modifying a database.

10. The method of claim 9, further comprising:

extracting data from the database as part of a decision process related to the portion or a larger design that incorporates the portion.

11. The method of claim 1 in which variation data is used to modify a manufacturing process.

12. The method of claim 1 in which variation data is used to determine a location for making a physical measurement within a wafer or die.

13. The method of claim 1 in which the context or environment is based at least in part upon an existing design, a pre-determined density, or random density, or random feature size and dimensions.

14. The method of claim 1 in which variations to analyze include within-die variation, within-wafer variation, or wafer-to-wafer variation.

15. The method of claim 1 in which the portion is positioned at different locations within the integrated circuit design.

16. The method of claim 15 in which a prediction is performed for the different locations regarding at least one physical result for the integrated circuit design.

17. The method of claim 16 in which a thickness or width prediction is performed.

18. The method of claim 16 in which the prediction is organized as a statistical distribution of values, combined with other predictions to create the statistical distribution or supplemented with one or more statistical indicators such as mean, variance, range, or standard deviation.

19. The method of claim 16 in which a thickness or width prediction is performed.

20. The method of claim 1 which is employed to simulate sensitivity of the portion to the context or environment.

21. The method of claim 20 applied to modify the integrated circuit design of the portion to make the integrated circuit design less sensitive to surrounding topography.

22. The method of claim 1 applied as part of library creation, modification or characterization.

23. The method of claim 1 used within an optimization loop to evaluate or modify a design.

24. The method of claim 1, further comprising generating data which is used to create one or more additional models.

25. The computer implemented method of claim 1, wherein a plurality of models are used to respectively characterize the variation of the one or more characteristics of the integrated circuit block feature within the context or environment at the plurality of locations.

26. The computer implemented method of claim 1, wherein the context or environment is not explicitly known for the integrated circuit block feature in the integrated circuit design.

27. The computer implemented method of claim 1, further comprising:

determining a distribution of the one or more characteristics of an integrated circuit block feature for at least the plurality of locations.

28. The computer implemented method of claim 1, wherein the context or environment comprises one or more prior designs that are shrunk to one or more smaller sizes for the integrated circuit block feature.

29. A computer program product that includes a non-transitory computer readable storage medium, the computer readable medium comprising a plurality of computer instructions which, when executed by a processor, cause the processor to execute a method for implementing an integrated circuit design, the method comprising:

using at least one processor that is programmed for performing a process, the process comprising;

identifying one or more models that characterize a variation in one or more characteristics of an integrated circuit block feature at each of a plurality of different locations, wherein,

the variation results resulting from first interactions between a fabrication process and the integrated circuit block feature that is placed at each of the plurality of locations for identification of the one or more models in a portion of the integrated circuit design;

identifying a context or environment for the integrated circuit block feature at each of the plurality of locations or a second plurality of locations;

simulating second interactions between the integrated circuit block feature and the context or environment at the each of the plurality of locations or the second plurality of locations at which the integrated circuit block feature is placed for performing the act of simulating the second interactions; and

at the each of the plurality of locations or the second plurality of locations, performing a prediction to predict a finished product of the integrated circuit design or an electronic design based at least in part upon a result of the act of simulating the second interactions.

30. The computer program product of claim 29, wherein a plurality of models are used to respectively characterize the variation of the one or more characteristics of the integrated circuit block feature within the context or environment at the plurality of locations.

31. The computer program product of claim 29, wherein the context or environment is not explicitly known for the integrated circuit block feature in the integrated circuit design.

32. The computer program product of claim 29, the process further comprising:

determining a distribution of the one or more characteristics of an integrated circuit block feature for at least the plurality of locations.

33. The computer program product of claim 29, wherein the context or environment comprises one or more prior designs that are shrunk to one or more smaller sizes for the integrated circuit block feature.

34. A system for implementing an integrated circuit design, comprising:

at least one processor that is programmed for performing a process, the process comprising;

identifying one or more models that respectively characterize a variation in one or more characteristics of an integrated circuit block feature at each of a plurality of locations, wherein

the variation results from first interactions between a fabrication process and the integrated circuit block feature that is placed at each of the plurality of locations for identification of the one or more models in a portion of the integrated circuit design;

identifying a context or environment the integrated circuit block feature at each of the plurality of locations or a second plurality of locations;

simulating second interactions between the integrated circuit block feature and the context or environment at the each of the plurality of locations or the second plurality of locations at which the integrated circuit block feature is placed for performing the act of simulating the second interactions; and

at the each of the plurality of locations or the second plurality of locations, performing a prediction to predict a finished product of the integrated circuit design or an electronic design based at least in part upon a result of the act of simulating the second interactions.

35. The system of claim 34, wherein a plurality of models are used to respectively characterize the variation of the one or more characteristics of the integrated circuit block feature within the context or environment at the plurality of locations.

36. The system of claim 34, wherein the context or environment is not explicitly known for the integrated circuit block feature in the integrated circuit design.

37. The system of claim 34, the computer system is further programmed for performing:

determining a distribution of the one or more characteristics of an integrated circuit block feature for at least the plurality of locations.

38. The system of claim 34, wherein the context or environment comprises one or more prior designs that are shrunk to one or more smaller sizes for the integrated circuit block feature.