Multithreaded computer system and multithread execution control method
First Claim
1. A multithreaded computer system, comprising:
- a plurality of processor elements, each processor element being operable to execute a process including a plurality of threads; and
a controller operable to switch threads to be executed in each processor element, said controller including;
a plurality of execution order registers, each execution order register being provided for a corresponding one of said processor elements, and which holds an execution order of threads to be executed by said corresponding processor elements;
a plurality of counters, each counter being provided for a corresponding one of said processor elements, each counter counting an execution time period for a thread that is being executed by said corresponding processor element and generating a timeout signal when the counted time reaches a limit assigned to the thread; and
a scheduler operable to switch the thread that is being executed to a thread to be executed by each processor element based on the execution order held in said execution order register and the timeout signal;
a status register indicating whether each processor element is in an execution state or in a stopped state; and
a plurality of possibility information holders provided corresponding to said processor elements, each possibility information holder holding possibility information as to whether parallel thread execution is possible, andwhen any of said processor elements has transitioned from the execution state to the stopped state, said scheduler further determines a thread available for parallel execution from among threads for other processor elements based on the possibility information, and causes said processor element in the stopped state to execute the determined thread,wherein the possibility information includes first information indicating whether or not parallel execution with another thread in the same process is possible and second information indicating whether or not execution by another processor element is possible, andeach of said possibility information holders includes;
a first register which holds the first information; and
a second register which holds the second information.
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Abstract
A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) and a parallel processor controller which switches threads in each PE. The parallel processor controller includes a plurality of execution order registers which hold, for each processor element, an execution order of threads to be executed; a plurality of counters which count an execution time for a thread that is being executed by each processor element and generate a timeout signal when the counted time reaches a limit assigned to the thread; and a thread execution scheduler which switches the thread that is being executed to the thread to be executed by each processor element based on an execution order held in the execution order register and the timeout signal.
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Citations
2 Claims
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1. A multithreaded computer system, comprising:
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a plurality of processor elements, each processor element being operable to execute a process including a plurality of threads; and a controller operable to switch threads to be executed in each processor element, said controller including; a plurality of execution order registers, each execution order register being provided for a corresponding one of said processor elements, and which holds an execution order of threads to be executed by said corresponding processor elements; a plurality of counters, each counter being provided for a corresponding one of said processor elements, each counter counting an execution time period for a thread that is being executed by said corresponding processor element and generating a timeout signal when the counted time reaches a limit assigned to the thread; and a scheduler operable to switch the thread that is being executed to a thread to be executed by each processor element based on the execution order held in said execution order register and the timeout signal; a status register indicating whether each processor element is in an execution state or in a stopped state; and a plurality of possibility information holders provided corresponding to said processor elements, each possibility information holder holding possibility information as to whether parallel thread execution is possible, and when any of said processor elements has transitioned from the execution state to the stopped state, said scheduler further determines a thread available for parallel execution from among threads for other processor elements based on the possibility information, and causes said processor element in the stopped state to execute the determined thread, wherein the possibility information includes first information indicating whether or not parallel execution with another thread in the same process is possible and second information indicating whether or not execution by another processor element is possible, and each of said possibility information holders includes; a first register which holds the first information; and a second register which holds the second information. - View Dependent Claims (2)
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Specification