Method of making a semiconductor chip assembly with a post/base heat spreader and vertical signal routing

• US 8,003,415 B2
• Filed: 09/13/2009
• Issued: 08/23/2011
• Est. Priority Date: 03/25/2008
• Status: Expired due to Fees

• Current Assignee: Bridge Semiconductor Corporation
• Original Assignee: Bridge Semiconductor Corporation
• Inventors: Lin, Charles W. C., Wang, Chia-Chung
• Primary Examiner(s): CAO, PHAT X
• Application Number:
  US12/558,527
• Publication Number:
  US 20100003788A1
• Time in Patent Office: 709 Days
• Field of Search: 438/22, 438/25, 438/26, 257/98, 257/99
• US Class Current: 438/22
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 33/483 Containers
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/642 characterized by the shape
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 2201/0352 : Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/09736 : Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2201/10106 : Light emitting diode [LED]
• CPC Class Codes: H05K 2201/10553 : Component over metal, i.e. metal plate in between bottom of component and surface of PCB
• CPC Class Codes: H05K 2203/0369 : Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/06 : the conductive material being removed chemically or electrolytically, e.g. by photo-etch process semi-additive methods H05K3/108
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence

Abstract

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate to form a gap in the aperture between the post and the substrate, then flowing the adhesive into and upward in the gap, solidifying the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader. The substrate includes first and second conductive layers and a dielectric layer therebetween, and the assembly provides the vertical signal routing between a pad at the first conductive layer and a terminal below the adhesive.

Claims

1. A method of making a semiconductor chip assembly, comprising:

providing a post, a base, an adhesive and a substrate, wherein

the substrate includes a first conductive layer, a second conductive layer and a dielectric layer therebetween,

the post is adjacent to the base, extends above the base in an upward direction, extends through an opening in the adhesive and extends into an aperture in the substrate,

the base extends below the post in a downward direction opposite the upward direction and extends laterally from the post in lateral directions orthogonal to the upward and downward directions,

the adhesive is mounted on and extends above the base, is sandwiched between the base and the substrate and is non-solidified,

the substrate is mounted on and extends above the adhesive, the first conductive layer extends above the dielectric layer, the dielectric layer extends above the second conductive layer, and

a gap is located in the aperture between the post and the substrate;

then

flowing the adhesive into and upward in the gap;

solidifying the adhesive;

then

mounting a semiconductor device on a heat spreader that includes the post and the base, wherein the semiconductor device overlaps or is overlapped by the post, the assembly includes a pad, a terminal, a routing line and first and second vias, the pad includes a selected portion of the first conductive layer, the routing line includes a selected portion of the second conductive layer, the first via extends through the dielectric layer between the first conductive layer and the routing line, the second via extends through the adhesive to the routing line, the terminal extends below the adhesive and a heat spreader includes the post and the base;

electrically connecting the semiconductor device to the pad or the terminal, thereby electrically connecting the semiconductor device to the other of the pad and the terminal, wherein an electrically conductive path between the pad and the terminal includes the first via, the routing line and the second via; and

thermally connecting the semiconductor device to the post or the base, thereby thermally connecting the semiconductor device to the other of the post and the base.

2. The method of claim 1, wherein providing the post and the base includes:

providing a metal plate;

forming an etch mask on the metal plate that selectively exposes the metal plate;

etching the metal plate in a pattern defined by the etch mask, thereby forming a recess in the metal plate that extends into but not through the metal plate; and

then

removing the etch mask, wherein the post is an unetched portion of the metal plate that protrudes above the base and is laterally surrounded by the recess, and the base is an unetched portion of the metal plate below the post and the recess.

3. The method of claim 1, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the base and the substrate; and

solidifying the adhesive includes curing the uncured epoxy.

4. The method of claim 1, wherein providing the substrate includes:

providing the routing line, including removing selected portions of the second conductive layer; and

then

forming the aperture.

5. The method of claim 1, wherein flowing the adhesive includes filling the gap with the adhesive.

6. The method of claim 1, wherein providing the pad includes:

grinding the post, the adhesive and the first conductive layer such that the post, the adhesive and the first conductive layer are laterally aligned with one another at a top lateral surface that faces in the upward direction; and

then

removing selected portions of the first conductive layer.

7. The method of claim 1, wherein providing the terminal includes:

forming an etch mask after solidifying the adhesive and before mounting the semiconductor device;

etching the base in a pattern defined by the etch mask; and

then

removing the etch mask, wherein the terminal includes an unetched portion of the base that is spaced and separated from and no longer part of the base.

8. The method of claim 1, wherein:

providing the first via includes forming a first hole through the first conductive layer and the dielectric layer to the routing line and then depositing a third conductive layer into the first hole and on the first conductive layer and the routing line; and

providing the second via includes forming a second hole through the base and the adhesive to the routing line and then depositing a fourth conductive layer into the second hole and on the base and the routing line.

9. The method of claim 1, including mounting the semiconductor device over the post, electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal, and thermally connecting the semiconductor device to the post, thereby thermally connecting the semiconductor device to the base.

10. The method of claim 9, wherein mounting the semiconductor device includes mounting a semiconductor chip over the post using a die attach, electrically connecting the semiconductor device includes providing a wire bond between the chip and the pad, and thermally connecting the semiconductor device includes providing the die attach between the chip and the post.

11. The method of claim 1, including mounting the semiconductor device below the base, electrically connecting the semiconductor device to the terminal, thereby electrically connecting the semiconductor device to the pad, and thermally connecting the semiconductor device to the base, thereby thermally connecting the semiconductor device to the post.

12. The method of claim 1, wherein:

the adhesive contacts the post, the base, the dielectric layer, the routing line, the second via and the terminal, covers and surrounds the post in the lateral directions and extends to peripheral edges of the assembly after the assembly is manufactured and detached from other assemblies in a batch; and

the base covers the post in the downward direction and supports the substrate after the assembly is manufactured and detached from the other assemblies in the batch.

13. The method of claim 1, including providing a cap on the post that extends above and is adjacent to and covers in the upward direction and extends laterally in the lateral directions from a top of the post and that overlaps and is adjacent to the adhesive after solidifying the adhesive and before mounting the semiconductor device, wherein the heat spreader includes the cap.

14. The method of claim 13, wherein providing the cap includes:

depositing a third conductive layer on the post, the adhesive and the first conductive layer; and

then

removing selected portions of the third conductive layer.

15. The method of claim 13, wherein providing the pad and the cap includes:

depositing a third conductive layer on the post, the adhesive and the first conductive layer;

forming an etch mask on the third conductive layer that selectively exposes the third conductive layer;

etching the first and third conductive layers using the etch mask to define the pad;

etching the third conductive layer using the etch mask to define the cap; and

then

removing the etch mask.

16. A method of making a semiconductor chip assembly, comprising:

providing a post and a base, wherein the post is adjacent to and integral with the base and extends above the base in an upward direction, and the base extends below the post in a downward direction opposite the upward direction and extends laterally from the post in lateral directions orthogonal to the upward and downward directions;

providing an adhesive, wherein an opening extends through the adhesive;

providing a substrate that includes first and second conductive layers and a dielectric layer therebetween, wherein a routing line includes a selected portion of the second conductive layer, and an aperture extends through the substrate;

mounting the adhesive on the base, including inserting the post through the opening, wherein the adhesive extends above the base and the post extends through the opening;

mounting the substrate on the adhesive, including inserting the post into the aperture, wherein the substrate extends above the adhesive, the first conductive layer extends above the dielectric layer, the dielectric layer extends above the second conductive layer, the post extends through the opening into the aperture, the adhesive is sandwiched between the base and the substrate and is non-solidified, and a gap is located in the aperture between the post and the substrate;

then

applying heat to melt the adhesive;

moving the base and the substrate towards one another, thereby moving the post upward in the aperture and applying pressure to the molten adhesive between the base and the substrate, wherein the pressure forces the molten adhesive to flow into and upward in the gap and the post and the molten adhesive extend above the dielectric layer;

applying heat to solidify the molten adhesive, thereby mechanically attaching the post and the base to the substrate;

then

providing a first via that extends from the first conductive layer through the dielectric layer to the routing line;

providing a second via that extends through the adhesive to the routing line;

providing a pad that extends above the dielectric layer, including removing selected portions of the first conductive layer;

providing a terminal that extends below the adhesive, including removing selected portions of the base;

providing a cap on the post that extends above and is adjacent to and covers in the upward direction and extends laterally in the lateral directions from a top of the post and that overlaps and is adjacent to the adhesive;

then

mounting a semiconductor chip on the cap, wherein a heat spreader includes the post, the base and the cap and the chip overlaps the post;

electrically connecting the chip to the pad, thereby electrically connecting the chip to the terminal, wherein an electrically conductive path between the pad and the terminal includes in sequence the first via, the routing line and the second via; and

thermally connecting the chip to the cap, thereby thermally connecting the chip to the base.

17. The method of claim 16, wherein providing the post and the base includes:

providing a metal plate;

forming an etch mask on the metal plate that selectively exposes the metal plate;

etching the metal plate in a pattern defined by the etch mask, thereby forming a recess in the metal plate that extends into but not through the metal plate; and

then

removing the etch mask, the post is an unetched portion of the metal plate that protrudes above the base and is laterally surrounded by the recess, and the base is an unetched portion of the metal plate below the post and the recess.

18. The method of claim 16, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the base and the substrate; and

solidifying the adhesive includes curing the uncured epoxy.

19. The method of claim 16, wherein forming the pad, the terminal and the vias includes:

forming a first hole through the first conductive layer and the dielectric layer to the routing line;

forming a second hole through the base and the adhesive to the routing line;

then

depositing a third conductive layer into the first hole and on the first conductive layer and the routing line;

depositing a fourth conductive layer into the second hole and on the base and the routing line;

then

removing selected portions of the first and third conductive layers using a first etch mask that defines the pad; and

removing selected portions of the fourth conductive layer and the base using a second etch mask that defines the terminal.

20. The method of claim 16, wherein providing the cap includes:

grinding the post, the adhesive and the first conductive layer such that the post, the adhesive and the first conductive layer are laterally aligned with one another at a top lateral surface that faces in the upward direction;

then

depositing a third conductive layer on the post, the adhesive and the first conductive layer; and

then

removing selected portions of the third conductive layer.

21. The method of claim 16, wherein providing the pad and the cap includes:

grinding the post, the adhesive and the first conductive layer such that the post, the adhesive and the first conductive layer are laterally aligned with one another at a top lateral surface that faces in the upward direction;

then

depositing a third conductive layer on the post, the adhesive and the first conductive layer;

forming an etch mask on the third conductive layer that selectively exposes the third conductive layer;

etching the first and third conductive layers using the etch mask to define the pad;

etching the third conductive layer using the etch mask to define the cap; and

then removing the etch mask.

22. The method of claim 16, wherein mounting the chip includes using a die attach between the chip and the cap, electrically connecting the chip includes providing a wire bond between the chip and the pad, and thermally connecting the chip includes providing the die attach between the chip and the cap.

23. The method of claim 16, wherein:

the adhesive contacts the post, the base, the dielectric layer, the routing line, the second via and the terminal, covers and surrounds the post in the lateral directions and extends to peripheral edges of the assembly after the assembly is manufactured and detached from other assemblies in a batch; and

the base covers the post in the downward direction and supports the substrate after the assembly is manufactured and detached from the other assemblies in the batch.

24. A method of making a semiconductor chip assembly, comprising:

providing a post and a base, wherein the post is adjacent to and integral with the base and extends above the base in an upward direction, and the base extends below the post in a downward direction opposite the upward direction and extends laterally from the post in lateral directions orthogonal to the upward and downward directions;

providing an adhesive, wherein an opening extends through the adhesive;

providing a substrate that includes first and second conductive layers and a dielectric layer therebetween, wherein a routing line includes a selected portion of the second conductive layer, and an aperture extends through the substrate;

mounting the adhesive on the base, including inserting the post through the opening, wherein the adhesive extends above the base and the post extends through the opening;

mounting the substrate on the adhesive, including inserting the post into the aperture, wherein the substrate extends above the adhesive, the first conductive layer extends above the dielectric layer, the dielectric layer extends above the second conductive layer, the post extends through the opening into the aperture, the adhesive is sandwiched between the base and the substrate and is non-solidified, and a gap is located in the aperture between the post and the substrate;

then

applying heat to melt the adhesive, thereby mechanically attaching the post and the base to the substrate;

moving the base and the substrate towards one another, thereby moving the post upward in the aperture and applying pressure to the molten adhesive between the base and the substrate, wherein the pressure forces the molten adhesive to flow into and upward in the gap and the post and the molten adhesive extend above the dielectric layer;

applying heat to solidify the molten adhesive;

then

forming a first hole through the first conductive layer and the dielectric layer to the routing line;

forming a second hole through the base and the adhesive to the routing line;

then

providing a first via, including depositing a third conductive layer into the first hole and on the post, the first conductive layer, the adhesive and the routing line;

providing a second via, including depositing a fourth conductive layer into the second hole and on the base and the routing line;

then

providing a pad that extends above the dielectric layer, including removing selected portions of the first and third conductive layers;

providing a terminal that extends below the adhesive, including removing selected portions of the base and the fourth conductive layer;

providing a cap on the post, including removing selected portions of the third conductive layer, wherein the cap extends above and is adjacent to and covers in the upward direction and extends laterally in the lateral directions from a top of the post;

then

mounting a chip on the cap, wherein a heat spreader includes the post, the base and the cap and the chip overlaps the post;

electrically connecting the chip to the pad, thereby electrically connecting the chip to the terminal, wherein an electrically conductive path between the pad and the terminal includes in sequence the first via, the routing line and the second via; and

thermally connecting the chip to the cap, thereby thermally connecting the chip to the base.

25. The method of claim 24, wherein:

providing the third and fourth conductive layers includes simultaneously plating the third and fourth conductive layers;

removing the selected portions of the first, third and fourth conductive layers and the base includes simultaneously etching the first, third and fourth conductive layers and the base;

the adhesive contacts the post, the base, the dielectric layer, the routing line, the second via and the terminal, covers and surrounds the post in the lateral directions and extends to peripheral edges of the assembly after the assembly is manufactured and detached from other assemblies in a batch; and

the base covers the post in the downward direction and supports the substrate after the assembly is manufactured and detached from the other assemblies in the batch.