Methods for forming anti-reflection structures for CMOS image sensors

• US 8,003,425 B2
• Filed: 05/14/2008
• Issued: 08/23/2011
• Est. Priority Date: 05/14/2008
• Status: Active Grant

• Current Assignee: Smartsens Technology (Cayman) Co., Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Ellis-Monaghan, John J., Adkisson, James W., Musante, Charles F.
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Singal; Ankush K
• Application Number:
  US12/120,459
• Publication Number:
  US 20090286346A1
• Time in Patent Office: 1,196 Days
• Field of Search: 257/E31.13, 257/436, 257/59, 257/72, 257/222, 257/229, 257/258, 257/292, 257/E31.079, 257/E31.123, 257/290, 257/462, 438/241, 438 60- 65, 438 72- 75
• US Class Current: 438/65
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

Claims

1. A method of forming a semiconductor structure comprising:

providing a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer, a buried insulator layer, and a handle substrate;

forming a photodiode on a top surface of said semiconductor layer;

removing said handle substrate and exposing a bottom surface of said buried insulator layer; and

forming an array of protuberances consisting of a material selected from silicon oxide, silicon nitride, or aluminum oxide at said bottom surface of said buried insulator layer, wherein a top surface of said buried insulator layer abuts a bottom surface of said semiconductor layer, each of said array of protuberances has a shape of a cone having a monotonically decreasing cross-sectional area as a function of a vertical distance from a base of said cone, and wherein a height of said cone is from about 40 nm to about 480 nm.

2. The method of claim 1, further comprising:

applying self-assembling block copolymers directly on said bottom surface of said buried insulator layer;

annealing said self-assembling block copolymers and inducing formation of cylindrical polymeric blocks and a polymeric block matrix surrounding said cylindrical polymeric blocks;

removing said cylindrical polymeric blocks selective to said polymeric block matrix; and

etching exposed portions of said buried insulator layer employing said polymeric block matrix as an etch mask, wherein said array of protuberances is formed by said etching.

3. The method of claim 1, wherein said array of protuberances consists of silicon nitride or aluminum oxide.

4. A method of forming a semiconductor structure comprising:

providing a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer, a buried insulator layer, and a handle substrate;

forming a photodiode on a top surface of said semiconductor layer;

forming a transistor directly on said top surface of said semiconductor layer, wherein a source of said transistor is of integral construction with said photodiode;

forming a shallow trench isolation region directly beneath said top surface of said semiconductor layer;

removing said handle substrate and exposing a bottom surface of said buried insulator layer; and

forming an array of protuberances at said bottom surface of said buried insulator layer, wherein a top surface of said buried insulator layer abuts a bottom surface of said semiconductor layer.

5. A method of forming a semiconductor structure comprising:

providing a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer, a buried insulator layer, and a handle substrate;

forming a photodiode on a top surface of said semiconductor layer;

removing said handle substrate and exposing a bottom surface of said buried insulator layer; and

forming an array of protuberances at said bottom surface of said buried insulator layer, wherein a top surface of said buried insulator layer abuts a bottom surface of said semiconductor layer, wherein each of said array of protuberances has a shape of a cone having a monotonically decreasing cross-sectional area as a function of a vertical distance from a base of said cone, and wherein a height of said cone is from about 40 nm to about 480 nm.

6. A method of forming a semiconductor structure comprising:

providing a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer, a buried insulator layer, and a handle substrate;

forming a photodiode on a top surface of said semiconductor layer;

removing said handle substrate and exposing a bottom surface of said buried insulator layer; and

applying self-assembling block copolymers directly on said bottom surface of said buried insulator layer;

annealing said self-assembling block copolymers and inducing formation of cylindrical polymeric blocks and a polymeric block matrix surrounding said cylindrical polymeric blocks;

removing said cylindrical polymeric blocks selective to said polymeric block matrix;

etching exposed portions of said buried insulator layer employing said polymeric block matrix as an etch mask; and

foaming an array of protuberances at said bottom surface of said buried insulator layer, wherein a top surface of said buried insulator layer abuts a bottom surface of said semiconductor layer, wherein said array of protuberances is formed by said etching.

7. The method of claim 6, wherein said self-assembling block copolymers contains a first polymeric block component and a second polymeric block component that are immiscible with each other.

8. The method of claim 6, wherein said self-assembling block copolymers comprises at least one of polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-block-polyisoprene (PS-b-PI), polystyrene-block-polybutadiene (PS-b-PBD), polystyrene-block-polyvinylpyridine (PS-b-PVP), polystyrene-block-polyethyleneoxide (PS-b-PEO), polystyrene-block-polyethylene (PS-b-PE), polystyrene-b-polyorganosilicate (PS-b-POS), polystyrene-block-polyferrocenyldimethylsilane (PS-b-PFS), polyethyleneoxide-block-polyisoprene (PEO-b-PI), polyethyleneoxide-block-polybutadiene (PEO-b-PBD), polyethyleneoxide-block-polymethylmethacrylate (PEO-b-PMMA), polyethyleneoxide-block-polyethylethylene (PEO-b-PEE), polybutadiene-block-polyvinylpyridine (PBD-b-PVP), and polyisoprene-block-polymethylmethacrylate (PI-b-PMMA).

9. The method of claim 7, wherein said polymeric block matrix comprising said first polymeric block component and said cylindrical polymeric blocks comprises said second polymeric block component.

10. A method of forming a semiconductor structure comprising:

providing a semiconductor-on-insulator (SOI) substrate comprising a semiconductor layer, a buried insulator layer, and a handle substrate;

forming a photodiode on a top surface of said semiconductor layer;

forming a transistor directly on said top surface of said semiconductor layer, wherein a source of said transistor is of integral construction with said photodiode;

removing said handle substrate and exposing a bottom surface of said buried insulator layer; and

forming an array of protuberances at said bottom surface of said buried insulator layer, wherein a top surface of said buried insulator layer abuts a bottom surface of said semiconductor layer.

11. The method of claim 10, wherein each of said array of protuberances has a shape of a cone having a monotonically decreasing cross-sectional area as a function of a vertical distance from a base of said cone, and wherein a height of said cone is from about 40 nm to about 480 nm.

12. The method of claim 10, further comprising:

applying self-assembling block copolymers directly on said bottom surface of said buried insulator layer;

annealing said self-assembling block copolymers and inducing formation of cylindrical polymeric blocks and a polymeric block matrix surrounding said cylindrical polymeric blocks;

removing said cylindrical polymeric blocks selective to said polymeric block matrix; and

etching exposed portions of said buried insulator layer employing said polymeric block matrix as an etch mask, wherein said array of protuberances is formed by said etching.