Methods of manufacturing a semiconductor device using a layer suspended across a trench

• US 8,003,487 B2
• Filed: 12/16/2008
• Issued: 08/23/2011
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Katana Silicon Technologies LLC (Tanit Ventures Inc.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Sang-Sup, Cho, Du-Hyun, Song, Jong-Heui, Yoo, Seung-Joo, Kang, Tae-Woo
• Primary Examiner(s): Ghyka; Alexander G
• Application Number:
  US12/335,831
• Publication Number:
  US 20090162989A1
• Time in Patent Office: 980 Days
• Field of Search: 438/427, 438/780, 438/781
• US Class Current: 438/427
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming first patterns separated from each other by a first width and second patterns separated from each other by a second width wider than the first width, on a substrate;

etching the substrate using the first patterns and the second patterns as an etching mask to form a first trench having a first depth and a preliminary second trench having a second depth;

forming a sacrificial layer to cover the first patterns and fill up a space between the first patterns while simultaneously filling up a space between the second patterns and exposing at least a floor of the preliminary second trench; and

etching the substrate using the sacrificial layer as an etching mask to form a second trench having a third depth deeper than the second depth,

wherein the sacrificial layer is formed by a polymer attachment process using a gas for forming the polymer; and

wherein the polymer attachment process is performed at a temperature of about 500°

C. to about 800°

C.

2. The method of claim 1, wherein the sacrificial layer is formed using a polymer including carbon.

3. The method of claim 2, wherein the polymer including carbon includes polyethylene, polyvinyl fluoride and/or polyvinylidene fluoride.

4. The method of claim 1, wherein the gas for forming the polymer includes ethylene, methyl fluoride and/or methyl difluoride.

5. The method of claim 1, wherein the substrate includes a cell region and a peripheral region and the first trench is formed in the cell region and the second trench is formed in the peripheral region.

6. The method of claim 1, wherein a ratio between the first depth and the third depth is in a range of about 1:

1.5 to about 1;

2.5.

7. The method of claim 1, further comprising removing the sacrificial layer.

8. The method of claim 7, wherein the sacrificial layer is removed by an ashing process and/or a stripping process.

9. The method of claim 1, wherein the first patterns and the second patterns are formed using a material having an etching selectivity with respect to the substrate.

10. The method of claim 7, further comprising:

forming a field insulation layer on the first patterns and the second patterns to fill up the first trench and the second trench;

partially removing the field insulation layer until the first patterns and the second patterns are exposed to form a first field insulation layer pattern and a second field insulation layer pattern defining an active region; and

forming a conductive structure on the active region.

11. The method of claim 10, wherein the substrate includes a cell region and a peripheral region and the first field insulation layer pattern is formed in the cell region to define the active region in the cell region and the second field insulation layer pattern is formed in the peripheral region to define the active region in the peripheral region.

12. The method of claim 11, wherein the conductive structure fanned on the active region in the cell region includes a tunnel insulation layer, a floating gate electrode, a dielectric layer pattern and a control gate electrode.

13. The method of claim 11, wherein the conductive structure formed on the active region in the peripheral region includes an insulation layer pattern and a conductive layer pattern.