Single poly CMOS imager

• US 8,003,506 B2
• Filed: 06/26/2009
• Issued: 08/23/2011
• Est. Priority Date: 10/21/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Picardat; Kevin M
• Assistant Examiner(s): Au; Bac H
• Application Number:
  US12/492,765
• Publication Number:
  US 20090298272A1
• Time in Patent Office: 788 Days
• Field of Search: 438/60, 438 73- 79, 438/144, 438/279, 438/585, 438/587, 438/595
• US Class Current: 438/587
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Claims

1. A method for fabricating a semiconductor device comprising:

forming a conductive material over a substrate;

forming a resist material on the conductive material;

patterning the resist material, leaving a portion of the conductive material exposed through the patterned resist layer;

partially etching the conductive material using the patterned resist material as a mask such that a plurality of first portions of the conductive material have a first thickness and a plurality of second portions of the conductive material have a second thickness that is greater than the first thickness, each second portion having a first width and being separated from each adjacent second portion by a first distance;

removing the patterned resist material;

forming spacers on sidewalls of the plurality of second portions and over the plurality of first portions;

etching the exposed conductive material to substantially remove the exposed portions of the plurality of first portions of the conductive material;

forming an insulating material on the plurality of second portions to form a plurality of gate structures; and

doping a region between two adjacent gate structures.

2. The method of claim 1, wherein the first thickness is about half of the second thickness.

3. The method of claim 1, wherein doping the region between two adjacent gate structures is performed by implanting into the region a concentration of ions in the range of about 3×

10¹¹ ions/cm² to about 1×

10¹⁴ ions/cm².

4. The method of claim 1, wherein doping the region between two adjacent gate structures is performed by implanting into the region a concentration of ions in the range of about 1×

10¹² ions/cm² to about 1×

10¹³ ions/cm².

5. The method of claim 1, wherein doping the region between two adjacent gate structures is performed by implanting into the region a concentration of ions in the range of about 3×

10¹¹ ions/cm² to about 1×

10¹⁴ ions/cm².

6. The method of claim 1, wherein doping the region between two adjacent gate structures is performed by implanting into the region ions in the range of about 1×

10¹² ions/cm² to about 1×

10¹³ ions/cm².

7. The method of claim 1, wherein a distance between two adjacent gate structures is in the range of approximately 100 Angstroms to approximately 2000 Angstroms.

8. The method of claim 1, wherein a distance between two adjacent gate structures is in the range of approximately 300 Angstroms to approximately 1000 Angstroms.

9. The method of claim 1, wherein the conductive material is selected from the group consisting of:

polysilicon, silicide, metal, polysilicon and silicide, and polysilicon and metal.

10. A method for fabricating a semiconductor device comprising:

forming a conductive material over a substrate;

partially etching a first portion of the conductive material such that the first portion of the conductive material has a first thickness and a second portion of the conductive material has a second thickness that is greater than the first thickness;

forming a dielectric material to be located only on sidewalls of the second portion and over the first portion;

etching the exposed conductive material to substantially remove the exposed portions of the first portion of the conductive material, wherein etching the exposed conductive material comprises reducing the second thickness of the second portion of the conductive material; and

forming an insulating material on the plurality of second portions to form a gate structure.

11. The method of claim 10, wherein the first thickness is about half of the second thickness.

12. The method of claim 10, further comprising, prior to partially etching a first portion of the conductive material, forming a resist material on the conductive material and patterning the resist material to leave the first portion of the conductive material exposed through the patterned resist layer.