Conductive trace with reduced RF impedance resulting from the skin effect

• US 8,004,061 B1
• Filed: 07/23/2004
• Issued: 08/23/2011
• Est. Priority Date: 08/15/2002
• Status: Expired due to Fees

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Drury, Robert, Mian, Michael, Johnson, Peter, Hopper, Peter J., Hwang, Kyuwoon
• Primary Examiner(s): Im; Junghwa M
• Application Number:
  US10/897,901
• Time in Patent Office: 2,587 Days
• Field of Search: 257/531, 257/781, 257/528, 257/774, 257/758, 257/E23.152
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).

Claims

1. A semiconductor device comprising:

a layer of insulation material formed over a semiconductor substrate; and

a conductive trace that contacts the layer of insulation material, the conductive trace having;

a conductive base region having a length substantially greater than a width;

a first conductive region having a U-shape with a base section that touches the conductive base region, a left sidewall that touches the base section, and a right sidewall that touches the base section; and

a second conductive region having a U-shape with a base section that touches the base section of the first conductive region, a left sidewall that touches the base section of the second conductive region, and a right sidewall that touches the base section of the second conductive region, the left sidewall of the first conductive region and the left sidewall of the second conductive region being laterally electrically isolated, the right sidewall of the first conductive region and the right sidewall of the second conductive region being laterally electrically isolated.

2. The semiconductor device of claim 1 wherein only isolation material lies laterally between the right sidewalls of the first and second conductive regions and the left sidewalls of the first and second conductive regions.

3. The semiconductor device of claim 1 wherein the right sidewalls of the first and second conductive regions and the left sidewalls of the first and second conductive regions have top surfaces that lie in a same horizontal plane.

4. The semiconductor device of claim 1 wherein the right sidewalls of the first and second conductive regions and the left sidewalls of the first and second conductive regions are substantially normal to a top surface of the conductive base region.

5. The semiconductor device of claim 1 wherein the right sidewalls of the first and second conductive regions and the left sidewalls of the first and second conductive regions have top surfaces that extend along the length of the base region.

6. The semiconductor device of claim 5 wherein only isolation material lies laterally between the right sidewalls of the first and second conductive regions and the left sidewalls of the first and second conductive regions.

7. The semiconductor device of claim 5 wherein the right sidewalls of the first and second conductive regions and the left sidewalls of the first and second conductive regions are substantially normal to a top surface of the conductive base region.

8. The semiconductor device of claim 1 and further comprising a third conductive region that touches the base section of the second conductive region.

9. The semiconductor device of claim 8 wherein the third conductive region, the right sidewalls of the first and second conductive regions, and the left sidewalls of the first and second conductive regions have top surfaces that lie in a same horizontal plane.

10. The semiconductor device of claim 1 and further comprising a non-conductive spacer touching a top surface of the base section of the first conductive region that extends horizontally from the left sidewall of the first conductive region to the second conductive region, and lying between the left sidewall of the first conductive region and the base section of the second conductive region such that a single horizontal plane that lies below a top surface of the base section of the second conductive region passes through the left sidewall of the first conductive region, the non-conductive spacer, and the base section of the second conductive region.

11. The semiconductor device of claim 10 wherein:

the non-conductive spacer touches the left sidewall of the first conductive region and the left sidewall of the second conductive region; and

the top surface of the base section of the first conductive region that extends horizontally from the left sidewall of the first conductive region to the second conductive region lies substantially in a first horizontal plane.

12. The semiconductor device of claim 11 wherein a top surface of the left sidewall and a top surface of the right sidewall of the first conductive region, and a top surface of the left sidewall and a top surface of the right sidewall of the second conductive region each lie substantially in a second horizontal plane.

13. The semiconductor device of claim 12 and further comprising a non-conductive structure touching the top surface of the base section of the second conductive region, the top surface of the base section of the second conductive region lying in a third horizontal plane, the third horizontal plane lying between the first and second horizontal planes, the non-conductive structure touching no portion of the base section of the second conductive region that lies below the top surface of the base section of the second conductive region, no portion of the non-conductive structure lying above the second horizontal plane.

14. The semiconductor device of claim 12 wherein a vertical distance measured from the top surface of the left sidewall of the second conductive region to the top surface of the base section of the first conductive region is greater than a vertical distance measured from the top surface of the left sidewall of the second conductive region to the top surface of the base section of the second conductive region.

15. A semiconductor device comprising:

an insulation structure;

an interconnect structure that touches the insulation structure, the interconnect structure having;

a base structure being conductive and having a top surface;

a first U-shaped structure being conductive and having a first horizontal portion and a first vertical portion that touches the first horizontal portion, the first horizontal portion having a bottom surface and a top surface, the bottom surface of the first horizontal portion touching the top surface of the base structure;

a second U-shaped structure being conductive and having a second horizontal portion and a second vertical portion that touches the second horizontal portion, the second horizontal portion having a bottom surface and a top surface, the bottom surface of the second horizontal portion touching the top surface of the first horizontal portion; and

a non-conductive spacer touching the first vertical portion, the second vertical portion, and the top surface of the first horizontal portion that extends horizontally from the first vertical portion to the second U-shaped structure, and lying between the first vertical portion and the second horizontal portion such that a single horizontal plane that lies below the top surface of the second horizontal portion passes through the first vertical portion, the non-conductive spacer, and the second horizontal portion.

16. The semiconductor device of claim 15 and further comprising a non-conductive structure that touches the second vertical portion and the top surface of the second horizontal portion, the non-conductive structure being horizontally spaced apart from the non-conductive spacer by the second vertical portion, the non-conductive structure touching no portion of the second horizontal portion that lies below the top surface of the second horizontal portion, no portion of the non-conductive structure lying above a top surface of the second vertical portion.

17. The semiconductor device of claim 15 wherein a vertical distance measured from a top surface of the second vertical portion to the top surface of the first horizontal portion is greater than a vertical distance measured from the top surface of the second vertical portion to the top surface of the second horizontal portion.

18. A semiconductor device comprising:

an insulation structure;

an interconnect structure that touches the insulation structure, the interconnect structure having;

a base structure being conductive and having a top surface;

a first U-shaped structure being conductive and having a first horizontal portion and a first vertical portion that touches the first horizontal portion, the first horizontal portion having a bottom surface and a top surface, the bottom surface of the first horizontal portion touching the top surface of the base structure, the first vertical portion having a top surface;

a second U-shaped structure being conductive and having a second horizontal portion and a second vertical portion that touches the second horizontal portion, the second horizontal portion having a bottom surface and a top surface, the bottom surface of the second horizontal portion touching the top surface of the first horizontal portion, the second vertical portion having a top surface, the top surface of the first vertical portion and the top surface of the second vertical portion lying substantially in a first horizontal plane;

a non-conductive spacer touching the top surface of the first horizontal portion that extends horizontally from the first vertical portion to the second U-shaped structure, the top surface of the first horizontal portion that extends horizontally from the first vertical portion to the second U-shaped structure lying substantially in a second horizontal plane; and

a non-conductive structure touching the top surface of the second horizontal portion, the top surface of the second horizontal portion lying substantially in a third horizontal plane, the third horizontal plane lying between the first and second horizontal planes, the non-conductive structure touching no portion of the second horizontal portion that lies below the top surface of the second horizontal portion, no portion of the non-conductive structure lying above the top surface of the second vertical portion.

19. The semiconductor device of claim 18 wherein:

the non-conductive spacer touches the first vertical portion and the second vertical portion; and

the non-conductive structure is horizontally spaced apart from the non-conductive spacer by the second vertical portion.

20. The semiconductor device of claim 18 wherein a vertical distance measured from the top surface of the second vertical portion to the top surface of the first horizontal portion is greater than a vertical distance measured from the top surface of the second vertical portion to the top surface of the second horizontal portion.