Post passivation interconnection schemes on top of IC chip

• US 8,004,088 B2
• Filed: 09/13/2007
• Issued: 08/23/2011
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/854,552
• Publication Number:
  US 20080001300A1
• Time in Patent Office: 1,440 Days
• Field of Search: 257/773, 257/690, 257/700, 257/774
• US Class Current: 257/773
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

a driver, receiver or I/O circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;

a first via in said dielectric layer and vertically over said first internal circuit, wherein said first via is connected to said first internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;

a second via in said passivation layer, wherein said second via is connected to said first interconnecting structure;

a third via in said passivation layer and vertically over said first via, wherein said third via is connected to said first via; and

a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.

2. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said second internal circuit, and a fourth via in said passivation layer, wherein said fourth via is connected to said second and third interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

3. The chip of claim 2 further comprising a third internal circuit in or on said silicon substrate, wherein said third internal circuit is connected to said second internal circuit through said third interconnecting structure, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

4. The chip of claim 1 further comprising an ESD circuit in or on said silicon substrate, and a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.

5. The chip of claim 4, wherein said third interconnecting structure provides an access to an external clock for said ESD circuit and for said second terminal.

6. The chip of claim 4, wherein said third interconnecting structure provides an access to an external signal for said ESD circuit and for said second terminal.

7. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

a driver, receiver or I/O circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;

a first via in said dielectric layer and vertically over said first internal circuit, wherein said first via is connected to said first internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;

a polymer layer over said passivation layer;

a second via in said polymer layer, wherein said second via is connected to said first interconnecting structure;

a third via in said polymer layer and vertically over said first via, wherein said third via is connected to said first via; and

a second interconnecting structure in said polymer layer and over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.

8. The chip of claim 7 further comprising a second internal circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said second internal circuit, and a fourth via in said polymer layer, wherein said fourth via is connected to said second and third interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

9. The chip of claim 7 further comprising an ESD circuit in or on said silicon substrate, and a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.

10. The chip of claim 9, wherein said third interconnecting structure provides an access to an external clock for said ESD circuit and for said second terminal.

11. The chip of claim 9, wherein said third interconnecting structure provides an access to an external signal for said ESD circuit and for said second terminal.

12. The chip of claim 7, wherein said polymer layer has a thickness greater than 2 micrometers.

13. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

a driver, receiver or I/O circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said drive, receiver or I/O circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;

a first via in said passivation layer, wherein said first via is connected to said first inter connecting structure;

a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;

a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first terminal is connected to said first internal circuit though, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure; and

an external connection point connected to a second terminal of said driver, receiver or I/O circuit, wherein said driver, receiver or I/O circuit is connected in series between said first interconnecting structure and said external connection point.

14. The chip of claim 13 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, wherein said first terminal is connected to said second internal circuit though, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.

15. The chip of claim 14 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first and second internal circuits are connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said first terminal is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.

16. The chip of claim 13 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit though, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said first terminal is connected to said second internal circuit through, in sequence, said first inter connecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.

17. The chip of claim 13 further comprising an ESD circuit in or on said silicon substrate, wherein said external connection point is connected to said ESD circuit.

18. The chip of claim 17, wherein said external connection point provides an access to an external clock for said ESD circuit and for said second terminal.

19. The chip of claim 17, wherein said external connection point provides an access to an external signal for said ESD circuit and for said second terminal.

20. The chip of claim 13 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said third interconnecting structure.