Phase interpolator system and associated methods

• US 8,004,335 B2
• Filed: 02/11/2008
• Issued: 08/23/2011
• Est. Priority Date: 02/11/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Coteus, Paul W., Ferraiolo, Frank D., Dreps, Daniel M., Kim, Kyu-hyoun
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US12/028,973
• Publication Number:
  US 20090201064A1
• Time in Patent Office: 1,289 Days
• Field of Search: None
• US Class Current: 327/231
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 7/21 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 2005/00293 Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/15026 with asynchronously driven series connected output stages

Abstract

A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.

Claims

1. A phase interpolator system comprising:

a clock to provide a clock signal;

a control section in communication with said clock to regulate the strength of the clock signal; and

a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from said control section; and

wherein said control section includes at least one of a passive circuit element and an active circuit element.

2. The phase interpolator system of claim 1 wherein said passive circuit element includes at least one of a variable resistor, a variable capacitor, and a variable inductor.

3. The phase interpolator system of claim 1 wherein said active circuit element includes at least one of a variable buffer, a variable inverter, and a multiplexer.

4. The phase interpolator system of claim 1 wherein said generator circuit includes at least one of a poly-phase filter, a resistor-capacitor multi-pole poly-phase filter, a quadrature oscillator, an open loop quadrature oscillator, and a complementary metal-oxide-semiconductor open loop quadrature oscillator.

5. The phase interpolator system of claim 1 wherein said control section includes a weighting circuit.

6. The phase interpolator system of claim 5 wherein said weighting circuit includes at least one of a weighted inverter stage and a variable buffer.

7. The phase interpolator system of claim 1 said control section includes a phase rotation controller.

8. The phase interpolator system of claim 1 wherein said clock provides digital clock signals.

9. The phase interpolator system of claim 1 wherein said clock provides a clock signal having one phase.

10. A method to improve a phase interpolator system comprising:

providing a clock signal;

regulating the strength of the clock signal; and

producing an alternate clock signal based upon the strength of the clock signal; and

wherein regulating the strength of the clock signal uses at least one of a passive circuit element and an active circuit element.

11. The method of claim 10 wherein the passive circuit element includes at least one of a variable resistor, a variable capacitor, and a variable inductor.

12. The method of claim 10 wherein the active circuit element includes at least one of a variable buffer, a variable inverter, and a multiplexer.

13. The method of claim 10 wherein producing the alternate clock signal uses at least one of a poly-phase filter, a resistor-capacitor multi-pole poly-phase filter, a quadrature oscillator, an open loop quadrature oscillator, and a complementary metal-oxide-semiconductor open loop quadrature oscillator.

14. The method of claim 10 wherein regulating the strength of the clock signal is performed by a weighting circuit.

15. The method of claim 14 wherein the weighting circuit includes at least one of a weighted inverter stage and a variable buffer.

16. The method of claim 10 wherein the clock provides at least one of digital clock signals and a single phase clock signal.