Radio frequency amplifier with digital amplitude modulation and method for controlling the delivering of power

• US 8,004,368 B2
• Filed: 09/15/2009
• Issued: 08/23/2011
• Est. Priority Date: 09/15/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Palmisano, Guiseppe, Presti, Calogero Davide, Carrara, Francesco, Scuderi, Antonino
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US12/586,067
• Publication Number:
  US 20100109789A1
• Time in Patent Office: 707 Days
• Field of Search: 332/144, 332/145, 332/149, 332151-154, 330/10
• US Class Current: 332/149
• CPC Class Codes: H03C 1/00 Amplitude modulation H03C5/00, H03C7/00 take precedence
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04

Abstract

A digital amplitude modulator. The digital amplitude modulator is configured to modulate the amplitude of an input carrier signal based on input digital data and generate a corresponding output signal. The digital amplitude modulator includes a first variable gain amplifier for receiving the input carrier signal and generating a corresponding first amplified carrier signal, a second variable gain amplifier for receiving the input digital data and generating corresponding digital amplitude control data and a plurality of selectively activatable amplifier stages. Each amplifier stage receives a replica of the first amplified carrier signal and generates a corresponding second amplified carrier signal when activated. The output signal corresponds to a combination of the second amplified carrier signals generated by the activated amplifier stages.

Claims

1. A digital amplitude modulator for modulating the amplitude of an input carrier signal based on input digital data and generating a corresponding output signal, the digital amplitude modulator including:

a first variable gain amplifier for receiving the input carrier signal and generating a corresponding first amplified carrier signal;

a second variable gain amplifier for receiving the input digital data and generating corresponding digital amplitude control data;

a plurality of selectively activatable amplifier stages, each one receiving a replica of the first amplified carrier signal and generating a corresponding second amplified carrier signal when activated, the output signal corresponding to a combination of the second amplified carrier signals generated by the activated amplifier stages;

a driving circuit configured to receive the digital amplitude control data and activate a corresponding set of selected amplifier stages based on the digital amplitude control data, and

a power controller unit configured to adjust the power delivered by the digital amplitude modulator by setting a first amplifying gain of the first variable gain amplifier and a second amplifying gain of the second variable gain amplifier.

2. The digital amplitude modulator of claim 1, wherein:

in response to a request for decreasing the power delivered by the digital amplitude modulator, the power controller unit is configured to decrease the second amplifying gain if the resolution of the digital amplitude control data is higher than a minimum threshold, or decrease the first amplifying gain if the resolution of the digital amplitude control data is lower than or equal to the minimum threshold, and

in response to a request for increasing the power delivered by the digital amplitude modulator, the power controller unit is configured to increase the second amplifying gain if the amplitude of the first amplified carrier signal is higher than or equal to a maximum threshold, or increase the first amplifying gain if the amplitude of the first amplified carrier signal is lower than the maximum threshold.

3. The digital amplitude modulator of claim 1, wherein the plurality of selectively activatable amplifier stages includes:

a first set of amplifier stages, all the amplifier stages of the first set having a same base amplifying gain, and

a second set of amplifier stages, each amplifier stage of the second set having a respective fractional amplifying gain corresponding to a respective fraction of the base amplifier gain.

4. The digital amplitude modulator claim 1, wherein each amplifier stage includes:

a single gain stage having an input terminal configured to receive the replica of the first amplified carrier signal and an output terminal configured to provide the second amplified carrier signal, or

a sequence of gain stages each one having an input terminal and an output terminal, the input terminal of each gain stage in the sequence different from a first gain stage of the sequence being connected to the output terminal of the preceding gain stage in the sequence, the input terminal of the first gain stage being configured to receive the replica of the first amplified carrier signal, the output terminal of a last gain stage of the sequence being configured to provide the second amplified carrier signal.

5. The digital amplitude modulator of claim 4, wherein at least one gain stage of the amplifier stage includes:

a first transistor having a control terminal coupled with the input terminal through a first capacitor, a first conduction terminal coupled with a terminal providing a reference voltage and a second conduction terminal coupled with the output terminal, and

a first resistor having a first terminal coupled with a terminal providing a bias voltage through a first controlled switch and a second terminal coupled with the control terminal of the first transistor, wherein;

the control terminal of the first transistor is further coupled with a terminal providing the reference voltage through a second controlled switch, and

the first and the second controlled switches are controlled by the driving circuit based on the digital amplitude control data.

6. The digital amplitude modulator of claim 4, wherein at least one gain stage of the amplifier stage includes:

a second transistor of a first conductivity type having a control terminal coupled with the input terminal through a second capacitor and a second controlled switch, a first conduction terminal coupled with a terminal providing a reference voltage and a second conduction terminal coupled with the output terminal,

a third transistor of a second conductivity type opposite to the first conductivity type, the third transistor having a control terminal coupled with the input terminal through a third controlled switch, a first conduction terminal coupled with the second conduction terminal of the second transistor and a second conduction terminal coupled with a terminal providing a bias voltage, and

a second resistor having a first terminal coupled with the control terminal of the second transistor and a second terminal coupled with the output terminal, wherein

the control terminal of the third transistor is further coupled with a terminal providing the reference voltage through a fourth controlled switch and to the second conduction terminal of the third transistor through a fifth controlled switch, and

the second, third, fourth and fifth controlled switches are controlled by the driving circuit based on the digital amplitude control data.

7. The digital amplitude modulator of claim 4, wherein at least one gain stage of the amplifier stage includes:

a fourth transistor of a first conductivity type having a control terminal coupled with the input terminal through a third capacitor, a first conduction terminal coupled with a terminal providing a reference voltage and a second conduction terminal coupled with the output terminal,

a fifth transistor of a second conductivity type opposite to the first conductivity type, the fifth transistor having a control terminal coupled with the input terminal, a first conduction terminal coupled with the second conduction terminal of the fourth transistor and a second conduction terminal coupled with a terminal providing a bias voltage through a sixth controlled switch, and

a third resistor having a first terminal coupled with the control terminal of the fourth transistor and a second terminal coupled with the output terminal, wherein

the second terminal of the fourth transistor is further coupled with a terminal providing the reference voltage through a seventh controlled switch, and

the sixth and seventh controlled switches are controlled by the driving circuit based on the digital amplitude control data.

8. The digital amplitude modulator of claim 4, wherein at least one gain stage of the amplifier stage is a differential gain stage having a further input terminal and a further output terminal, said at least one gain stage including:

a sixth transistor of a first conductivity type having a control terminal coupled with the input terminal through a fourth capacitor, a first conduction terminal coupled with a terminal providing a reference voltage and a second conduction terminal coupled with the output terminal,

a seventh transistor of a second conductivity type opposite to the first conductivity type, the fifth transistor having a control terminal coupled with the input terminal, a first conduction terminal coupled with the second conduction terminal of the sixth transistor and a second conduction terminal coupled with a terminal providing a bias voltage through an eighth controlled switch,

a fourth resistor having a first terminal coupled with the control terminal of the sixth transistor and a second terminal coupled with the output terminal,

an eighth transistor of the first conductivity type having a control terminal coupled with the further input terminal through a fifth capacitor, a first conduction terminal coupled with a terminal providing a reference voltage and a second conduction terminal coupled with the further output terminal, and

a ninth transistor of the second conductivity type having a control terminal coupled with the further input terminal, a first conduction terminal coupled with the second conduction terminal of the eighth transistor and a second conduction terminal coupled with the second conduction terminal of the seventh transistor,

a fifth resistor having a first terminal coupled with the control terminal of the eighth transistor and a second terminal coupled with the further output terminal, wherein

the output terminal is coupled with the output terminal through a ninth controlled switch, and

the eighth and ninth controlled switches are controlled by the driving circuit based on the digital amplitude control data.

9. A method for operating a digital amplitude modulator configured to modulate the amplitude of an input carrier signal based on input digital data and generate a corresponding output signal and including a plurality of selectively activatable amplifier stages, the method comprising the following steps:

generating a first amplified carrier signal by multiplying the input carrier signal by a first amplifying gain,

generating digital amplitude control data by multiplying the input digital data by a second amplifying gain,

providing a replica of the first amplified carrier signal to each amplifier stage, each amplifier stage being configured to generate a corresponding second amplified carrier signal when activated,

activating a set of selected amplifier stages based on the digital amplitude control data, the output signal corresponding to a combination of the second amplified carrier signals generated by the activated amplifier stages,

adjusting the power delivered by the digital amplitude modulator by setting the first amplifying gain and the second amplifying gain.

10. The method of claim 9, wherein:

in response to a request for decreasing the power delivered by the digital amplitude modulator, the step of adjusting the power includes decreasing the second amplifying gain if the resolution of the digital amplitude control data is higher than a minimum threshold, or decreasing the first amplifying gain if the resolution of the digital amplitude control data is lower than or equal to the minimum threshold, and

in response to a request for increasing the power delivered by the digital amplitude modulator, the step of adjusting the power includes increasing the second amplifying gain if the amplitude of the first amplified carrier signal is higher than or equal to a maximum threshold, or increasing the first amplifying gain if the amplitude of the first amplified carrier signal is lower than the maximum threshold.

11. A digital amplitude modulator, comprising:

a variable gain amplifier adapted to receive a carrier signal and a digital amplitude control signal, the variable gain amplifier operable to apply a first gain to the carrier signal to generate a first amplified carrier signal and to apply a second gain to the digital amplitude control signal to generate an amplified digital amplitude control signal and to decode the amplified digital amplitude control signal to generate digital control signals, the second gain having a value that is independent of the value of the first gain;

a plurality of amplifier stages coupled to the variable gain amplifier, each amplifier stage receiving a replica of the first amplified carrier signal and a corresponding one of the digital control signals and operable when activated by the corresponding digital control signal to generate a corresponding second amplified carrier signal;

a combining circuit coupled to the plurality of amplifier stages, the combining circuit operable to generate an output signal having a value that is proportional to the sum of second amplified carrier signals provided by the activated amplifier stages; and

a power control circuit coupled to the variable gain amplifier and adapted to receive a power control command signal,

the power control circuit operable in a first mode responsive to the power control command signal indicating the power of the output signal should be decreased to reduce the second gain if a resolution of the amplified digital amplitude control signal is greater than a first threshold value and to reduce the first gain if the resolution of the amplified digital amplitude control signal is less than or equal to the first threshold value, and

the power control circuit operable in a second mode responsive to the power control command signal indicating the power of the output signal should be increased to raise the second gain if the first amplified carrier signal has an amplitude that has reached a second threshold value and to raise the first gain if the first amplified carrier signal has an amplitude that is less than the second threshold value.

12. The digital amplitude modulator of claim 11 wherein the variable gain amplifier is further operable to phase shift the first amplified input carrier signal relative to the input carrier signal.

13. The digital amplitude modulator of claim 11 wherein there are N+M amplifier stages, N amplifier stages having a unit gain A0 and M amplifier stages having fractional unit gains having a value less than the unit gain A0.

14. The digital amplitude modulator of claim 13 wherein the M amplifier stages have respective fractional unit gains given by A0/2X where X varies from 1 to M for these M amplifier stages.

15. The digital amplitude modulator of claim 11 wherein the variable gain amplifier comprises:

a first variable gain amplifier adapted to receive the carrier signal and apply the first gain to the carrier signal to generate the first amplified carrier signal;

a signal splitting circuit coupled to the first variable gain amplifier and operable responsive to the first amplified carrier signal to generate the replica of the first amplified carrier signal applied to each amplifier stage;

a second variable gain amplifier adapted to receive the digital amplitude control signal and operable to apply the second gain to the digital amplitude control signal to generate the amplified digital amplitude control signal; and

a digital decoder circuit coupled to the second variable gain amplifier to receive the amplified input signal data and to decode the amplified input signal data to generate the digital control signals.

16. The digital amplitude modulator of claim 11 wherein each amplifier stage comprises a single gain stage having an input node adapted to receive the replica of the first amplified carrier signal and an output node coupled to the combining circuit.

17. The digital amplitude modulator of claim 11 wherein each amplifier stage comprises a plurality of gain stages connected in series between an input node adapted to receive the replica of the first amplified carrier signal and an output node coupled to the combining circuit.

18. The digital amplitude modulator of claim 17 wherein each amplifier stage comprises:

a differential gain stage including,

a first capacitive element;

a first transistor having a control node coupled to a first input node through the first capacitive element, a first conduction node adapted to receive a reference voltage and a second conduction node coupled to a first output node;

a second transistor having a control node coupled to the first input node, a first conduction node coupled to the first output node and a second conduction node coupled to a biasing node;

a biasing transistor having a control node coupled to receive an enable signal, a first conduction node adapted to receive a supply voltage and a second conduction node coupled to the biasing node;

a first resistive element having a first node coupled to the control node of the first transistor and a second node coupled to the first output node;

a second capacitive element;

a third transistor having a control node coupled to a second input node through the second capacitive element, a first conduction node adapted to receive the reference voltage and a second conduction node coupled to a second output node;

a fourth transistor having a control node coupled to the second input node, a first conduction node coupled to the second output node and a second conduction node coupled to the biasing node;

a second resistive element having a first node coupled to the control node of the third transistor and a second node coupled to the second output node;

a fifth transistor having first and second conduction nodes coupled to the first and second output nodes, respectively, and having a control node coupled to receive the enable signal;

a control circuit adapted to receive a clocking signal and operable responsive to the clocking signal to generate the enable signal;

a second stage including,

a sixth transistor having a control node coupled to the first output node, a first conduction node adapted to receive the reference voltage and a second conduction node coupled to a first final output node;

a seventh transistor having a control node coupled to the second output node, a first conduction node adapted to receive the reference voltage and a second conduction node coupled to a second final output node

an eighth transistor having a control node coupled to the control circuit to receive the enable signal, a first conduction node adapted to receive the reference voltage and a second conduction node coupled to the control node of the sixth transistor; and

a ninth transistor having a control node coupled to the control circuit to receive the enable signal, a first conduction node adapted to receive the reference voltage and a second conduction node coupled to the control node of the seventh transistor.

19. An electronic system, comprising:

first and second digital amplitude modulators adapted to receive first and second carrier signals, respectively, the first and second carrier signals being in quadrature and each of the digital amplitude modulators comprising,

a variable gain amplifier adapted to receive the corresponding carrier signal and a digital amplitude control signal, the variable gain amplifier operable to apply a first gain to the carrier signal to generate a first amplified carrier signal and to apply a second gain to the digital amplitude control signal to generate an amplified digital amplitude control signal and to decode the amplified digital amplitude control signal to generate digital control signals, the second gain having a value that is independent of the value of the first gain;

a plurality of amplifier stages coupled to the variable gain amplifier, each amplifier stage receiving a replica of the first amplified carrier signal and a corresponding one of the digital control signals and operable when activated by the corresponding digital control signal to generate a corresponding second amplified carrier signal;

a combining circuit coupled to the plurality of amplifier stages, the combining circuit operable to generate an output signal having a value that is proportional to the sum of second amplified carrier signals provided by the activated amplifier stages;

a power control circuit coupled to the variable gain amplifier and adapted to receive a power control command signal,

the power control circuit operable in a first mode responsive to the power control command signal indicating the power of the output signal should be decreased to reduce the second gain if a resolution of the amplified digital amplitude control signal is greater than a first threshold value and to reduce the first gain if the resolution of the amplified digital amplitude control signal is less than or equal to the first threshold value, and

the power control circuit operable in a second mode responsive to the power control command signal indicating the power of the output signal should be increased to raise the second gain if the first amplified carrier signal has an amplitude that has reached a second threshold value and to raise the first gain if the first amplified carrier signal has an amplitude that is less than the second threshold value; and

a summing circuit operable to sum the output signals from the first and second digital amplitude modulators to generate an overall output signal.

20. The electronic system of claim 19 wherein the electronic system comprises a wireless mobile electronic device.

21. A method for operating a digital amplitude modulator, comprising:

multiplying a carrier signal by a first gain to generate an amplified carrier signal;

multiplying a digital amplitude control signal by a second gain to generate an amplified digital amplitude control signal;

splitting the amplified carrier signal to generate X corresponding split amplified carrier signals where X is an integer;

multiplying Y split amplified carrier signals by a corresponding stage gain where Y is an integer that is less than or equal to X and Y has a value determined from the amplified digital amplitude control signal;

combining the Y split amplified carrier signal to generate an output signal;

controlling the power of the output signal in a first mode when a power control command signal indicates the power of the output signal is to be decreased by,

lowering the second gain when a resolution of the amplified digital amplitude control signal is greater than a first threshold value,

lowering the first gain when the resolution of the digital amplitude control signal is less than or equal to the first threshold value; and

controlling the power of the output signal in a second mode when the power control command signal indicates the power of the output signal is to be increased by,

raising the second gain when the first amplified carrier signal has an amplitude that has reached a second threshold value, and

raising the first gain when the amplified carrier signal has an amplitude that is less than the second threshold value.

22. The method of claim 21 wherein multiplying the carrier signal by the first gain further comprising shifting a phase of the carrier signal.

23. The method of claim 21 wherein multiplying Y split amplified carrier signals comprises:

multiplying N split amplified carrier signals by a first stage gain where N is an integer that is less than Y and N is determined by the value of the amplified digital amplitude control signal; and

multiplying at least some of Y−

N amplified carrier signals by respective fractional stage gains, wherein each respective fractional stage gain has value that is a different fraction of the first gain and number of the Y−

N amplified carrier signals that are multiplied by fractional stage gains and the specific fractional stage gains utilized are determined by the amplified digital amplitude control signal.

24. The method of claim 21 wherein the carrier signal comprises an RF signal.

25. The method of claim 21 wherein the RF signal has a frequency in the range of 0.7 to 5.8 GHz.