Translation of register-combiner state into shader microcode

• US 8,004,523 B1
• Filed: 12/28/2007
• Issued: 08/23/2011
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Migdal, Amy J., Bastos, Rui M., Abdalla, Karim M., Cabral, Brian
• Primary Examiner(s): Chauhan; Ulka
• Assistant Examiner(s): PRENDERGAST, ROBERTA D
• Application Number:
  US11/966,905
• Time in Patent Office: 1,334 Days
• Field of Search: 345/426, 345/543, 345/559, 719/328
• US Class Current: 345/426
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/50 Lighting effects
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by the program instructions are allocated for processing in the shader program. The registers may be remapped for more efficient use of the register storage space.

Claims

1. A method of generating shader program instructions to control a fragment shader within a programmable graphics processing pipeline, wherein the programmable graphics processing pipeline includes a GPU driver and a combiner instruction processing unit (IPU), the method comprising:

receiving, at the GPU driver, a fixed function application programming interface (API) call to perform one or more combiner operations on pixel data;

converting, at the GPU driver, the fixed function API call into a fixed function state that represents the one or more combiner operations;

providing the fixed function state to the combiner instruction processing unit;

translating, at the combiner instruction processing unit, the fixed function state into at least one shader program instruction for performing the one or more combiner operations, wherein the at least one shader program instruction is suitable for execution by the fragment shader within the programmable graphics processing pipeline for shading one or more pixels for display; and

after translating the fixed function state into the at least one shader program instruction, providing the at least one shader program instruction to the fragment shader within the programmable graphics processing pipeline for execution.

2. The method of claim 1, further comprising the steps of:

determining a number of registers needed to execute the fixed function API call based on the fixed function state; and

allocating the number of registers prior to the translating of the fixed function state.

3. The method of claim 2, further comprising the step of remapping the number of registers to pack the registers and produce a register remap table.

4. The method of claim 1, further comprising the step of allocating registers for processing the at least one shader program instruction.

5. The method of claim 4, further comprising the step of remapping the registers to produce a register remap table.

6. The method of claim 5, wherein the remapping is performed within the programmable graphics processing pipeline.

7. The method of claim 1, further comprising the step of determining that a pixel packet for processing by the fragment shader within the programmable graphics processing pipeline is a first pixel packet received after a fixed function state change.

8. The method of claim 7, further comprising the step of blocking incoming pixel packets until the fragment shader within the programmable graphics processing pipeline becomes idle.

9. The method of claim 8, further comprising the steps of:

determining that the fragment shader within the programmable graphics processing pipeline is idle; and

accepting incoming pixel packets to process the incoming pixel packets using the fixed function state change.

10. The method of claim 1, wherein the fixed function API call is a combiner API call and the fixed function state is a combiner state bundle.

11. A method as in claim 1, further comprising executing the at least one shader program instruction for performing the fixed function API call using the fragment shader within the programmable graphics processing pipeline.

12. An apparatus for generating shader program instructions for performing an application programming interface (API) call to perform combiner operations, comprising:

a GPU driver stored in a memory configured to;

receive and store a set of fixed function states associated with an API call to perform one or more combiner operations on pixel data, wherein the set of fixed function state represents the one or more combiner operations, and

provide the fixed function states to the combiner instruction processing unit; and

a combiner instruction processing unit configured to;

generate the shader program instructions for performing the one or more combiner operations by translating the fixed function state into at least one shader program instruction, wherein the at least one shader program instruction is suitable for execution by a fragment shader within the programmable graphics processing pipeline for performing the combiner functions and produce one or more pixels for display, and

after translating the fixed function state into the at least one shader program instruction, provide the at least one shader program instruction to the fragment shader within the programmable graphics processing pipeline for execution.

13. The apparatus of claim 12, wherein the GPU driver is further configured to convert a fixed function API call into one or more fixed function state bundles that represent the fixed function state.

14. The apparatus of claim 12, further comprising a raster state machine coupled to the combiner instruction processing unit and configured to receive pixel packets and determine whether or not the pixel packets indicate a new fixed function program should be generated by detecting that a pixel packet is a first pixel packet received after a fixed function state change.

15. The apparatus of claim 14, wherein the raster state machine is further configured to block incoming pixel packets until the fragment shader within the programmable graphics processing pipeline becomes idle.

16. The apparatus of claim 15, wherein the raster state machine is further configured to accept incoming pixel packets to process the incoming pixel packets using the fixed function state change when the fragment shader within the programmable graphics processing pipeline becomes idle.

17. The apparatus of claim 12, wherein the combiner instruction processing unit is configured to determine and allocate a number of registers needed to execute the fixed function API call based on the fixed function state.

18. The apparatus of claim 17, wherein the combiner instruction processing unit is configured to remap the registers to pack the registers and produce a register remap table.

19. The apparatus of claim 12, wherein the fixed function API call is a combiner API call and the fixed function state bundle is a combiner state bundle.