Energy conditioning circuit arrangement for integrated circuit

• US 8,004,812 B2
• Filed: 06/07/2010
• Issued: 08/23/2011
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Primary Examiner(s): Jackson; Stephen W
• Application Number:
  US12/795,625
• Publication Number:
  US 20100307810A1
• Time in Patent Office: 442 Days
• Field of Search: 361/118
• US Class Current: 361/118
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/023 : using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/0237 : High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 2201/09236 : Parallel layout layout of balanced signal pairs H05K1/0245; superposed layout H05K2201/09672
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Claims

1. A substrate with conductive pathway arrangement, comprising:

a first conductive pathway having a first conductive area;

a second conductive pathway having a second conductive area;

a third conductive pathway having a third conductive area;

a fourth conductive pathway having a fourth conductive area;

a fifth conductive pathway having a fifth conductive area;

wherein said first conductive pathway, said third conductive pathway and said fifth conductive pathway are conductively connected to one another;

wherein said second conductive pathway and said fourth conductive pathway are electrically isolated from said first conductive pathway, said third conductive pathway and said fifth conductive pathway;

wherein a portion of said second area is substantially the same size as a portion of said fourth area, and wherein said third area is larger than said portion of said second area;

wherein said portion of said second area is between said first area and said third area, and wherein said portion of said fourth area is between said third area and said fifth area;

wherein said portion of said second area overlaps said portion of said fourth area; and

wherein said portion of said second area is completely shielded from said portion of said fourth area by said third area.

2. The substrate with conductive pathway arrangement of claim 1, further comprising:

a dielectric material; and

wherein said first area, said second area, said third area, said fourth area, and said fifth area are stacked and spaced apart from one another by said dielectric material.

3. The substrate with conductive pathway arrangement of claim 2, wherein said first conductive pathway, said third conductive pathway and said fifth conductive pathway are conductively connected to one another by a plurality of vias;

and

wherein said third area forms a central common portion of two common conductive pathway containers that surround said portion of said second area and said portion of said fourth area, said containers separating said portion of said second area and said portion of said fourth area from one another.

4. The substrate with conductive pathway arrangement as recited in claim 3, wherein said second conductive pathway and said fourth conductive pathway are electrically insulated from each other.

5. The substrate with conductive pathway arrangement as recited in claim 2, wherein said first conductive pathway, said third conductive pathway and said fifth conductive pathway are conductively connected to one another by a plurality of vias;

and

wherein said second conductive pathway and said fourth conductive pathway are electrically insulated from each other.