Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same

• US 8,004,893 B2
• Filed: 06/26/2009
• Issued: 08/23/2011
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jung-Dal, Sim, Jae-Sung
• Primary Examiner(s): Luu; Pho M
• Application Number:
  US12/492,209
• Publication Number:
  US 20100002516A1
• Time in Patent Office: 788 Days
• Field of Search: 365/185.17, 365/185.05, 365/185.02
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

Claims

1. A three-dimensional nonvolatile memory device, comprising:

a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series, said first plurality of string selection transistors comprising a first plurality of depletion-mode transistors and a first enhancement-mode transistor;

a second NAND-type string of EEPROM cells having a second plurality of string selection transistors therein electrically connected in series, said second plurality of string selection transistors comprising a second plurality of depletion-mode transistors and a second enhancement-mode transistor, said first enhancement-mode transistor stacked vertically relative to one of the second plurality of depletion-mode transistors and said second enhancement-mode transistor stacked vertically relative to one of the first plurality of depletion-mode transistors;

a first string selection line electrically connected to a gate electrode of the first enhancement-mode transistor and a gate electrode of the one of the second plurality of depletion-mode transistors; and

a second string selection line electrically connected to a gate electrode of the second enhancement-mode transistor and a gate electrode of the one of the first plurality of depletion-mode transistors;

wherein each of the first plurality of string selection transistors in said first NAND-type string of EEPROM cells is electrically coupled to a corresponding one of a plurality of string selection lines;

wherein each of the second plurality of string selection transistors in said second NAND-type string of EEPROM cells is electrically coupled to a corresponding one of the plurality of string selection lines;

wherein each of the first plurality of string selection transistors in said first NAND-type string of EEPROM cells is electrically coupled to only one of the plurality of string selection lines; and

wherein each of the second plurality of string selection transistors in said second NAND-type string of EEPROM cells is electrically coupled to only one of the plurality of string selection lines.

2. The memory device of claim 1, further comprising:

a first string selection plug electrically connecting a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors; and

a second string selection plug electrically connecting a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

3. A three-dimensional semiconductor device comprising:

a first interconnection structure;

a second interconnection structure; and

a plurality of cell strings connecting the first and second interconnection structures in parallel,

wherein each of the cell strings includes;

a plurality of memory cell transistors connected in series; and

a plurality of first selection transistors connecting in series the first interconnection structure and a memory cell transistor adjacent thereto;

first selection lines connecting gate electrodes of the first selection transistors

wherein one of the first selection transistors in one cell string is an enhancement mode transistor and the rest of the first selection transistors are depletion mode transistors; and

wherein the number of the first selection transistors connected to one of the first selection lines is one in each of the cell strings.

4. The three-dimensional semiconductor device of claim 3, wherein a position of the enhancement mode transistor among the first selection transistors varies according to a position of the cell string.

5. The three-dimensional semiconductor device of claim 3, wherein the enhancement mode transistors in each of the cell strings are connected to the respectively different first selection lines.

6. The three-dimensional semiconductor device of claim 3, wherein the number of the first selection transistors in each of the cell strings is at least the number of the cell strings connecting the first and second interconnection structures in parallel.

7. The three-dimensional semiconductor device of claim 3, further comprising at least one second selection transistor connecting in series the second interconnection structure and a memory cell transistor adjacent thereto.

8. A three-dimensional semiconductor device comprising:

a bit line plug and a common source line plug spaced apart from each other on a substrate;

a plurality of semiconductor patterns stacked sequentially on the substrate and connecting the bit line plug and the common source line plug in parallel; and

a plurality of string selection transistors disposed on the semiconductor patterns, respectively,

wherein the string selection transistors disposed on each of the semiconductor patterns include at least one enhancement mode transistor and at least one depletion mode transistor.

9. The three-dimensional semiconductor device of claim 8, wherein at least one of the string selection transistors in each of the semiconductor patterns is an enhancement mode transistor and the rest of the string selection transistors are depletion mode transistors.

10. The three-dimensional semiconductor device of claim 9, wherein a distance between the bit line plug and the enhancement mode transistor varies according to a stacking order of the semiconductor patterns.

11. The three-dimensional semiconductor device of claim 8, further comprising:

a plurality of string selection lines penetrating through the semiconductor patterns to be used as gate electrodes of the string selection transistors,

wherein a gate electrode of one enhancement mode string selection transistor is connected to one string selection line.

12. The three-dimensional semiconductor device of claim 8, wherein the enhancement mode string selection transistors disposed in each of the semiconductor patterns are connected to different string selection lines, respectively.

13. The three-dimensional semiconductor device of claim 8, wherein the number of the string selection transistors in each of the semiconductor patterns is at least the number of semiconductor patterns connecting the bit line plug and the common source line plug in parallel.

14. The three-dimensional semiconductor device of claim 8, wherein the semiconductor patterns are perpendicularly stacked and are horizontally arranged to be arranged three-dimensionally, and the three-dimensional semiconductor device further comprises an insulating material for filling the horizontally adjacent semiconductor patterns.

15. A method of fabricating the three-dimensional semiconductor device of claim 8, wherein the method comprises forming a plurality of semiconductor layers on the substrate, the step of forming the semiconductor layer comprising implanting selectively impurities in a region where the depletion mode transistors are formed.