Nonvolatile memory system, semiconductor memory and writing method

• US 8,004,905 B2
• Filed: 03/18/2010
• Issued: 08/23/2011
• Est. Priority Date: 07/09/1996
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tsuchiya, Osamu, Kubono, Shooji, Ishii, Tatsuya, Miwa, Hitoshi
• Primary Examiner(s): Nguyen; VanThu
• Assistant Examiner(s): Nguyen; Hien N
• Application Number:
  US12/726,485
• Publication Number:
  US 20100182847A1
• Time in Patent Office: 523 Days
• Field of Search: 365/185.18, 365/185.29, 365/185.24, 365/185.23, 365/185.3, 365/185.02
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory used in a nonvolatile memory apparatus by receiving an instruction from a control device in the nonvolatile memory apparatus, comprising:

a plurality of nonvolatile memory cells, each of which is capable of storing data in accordance with difference of a threshold voltage thereof;

a plurality of word lines, each of which is coupling with corresponding memory cells; and

a sequencer for controlling accessing to the nonvolatile memory cells in accordance with the instruction,

wherein the sequencer performs an erase operation in response to an erase instruction that the threshold voltage of all of the nonvolatile memory cells coupled with a selected word line move over a first boundary voltage indicating an erase state,

wherein the sequencer is capable of performing an program operation in response to a program instruction that the threshold voltage of first ones of the nonvolatile memory cells coupled with a selected word line move over a second boundary voltage indicating a program state from the erase state when second ones of the nonvolatile memory cells coupled with the selected word line have been in the program state.

2. A nonvolatile memory according to claim 1, further comprising:

terminals coupling with the control device for receiving the instruction; and

a command register for temporarily storing the instruction.

3. A nonvolatile memory according to claim 1,

wherein the sequencer performs a read operation in the erase operation for checking whether the threshold voltage of all of the nonvolatile memory cells coupled with the selected word line have moved over the first boundary voltage or not.

4. A nonvolatile memory according to claim 1,

wherein the sequencer performs a read operation in the program operation for checking whether the threshold voltage of the first ones of the nonvolatile memory cells coupled with the selected word line have moved over the second boundary voltage or not.

5. A nonvolatile memory used in a nonvolatile memory apparatus by receiving an instruction from a control device in the nonvolatile memory apparatus, comprising:

a plurality of nonvolatile memory cells, each of which is capable of storing data in accordance with difference of a threshold voltage thereof;

a plurality of word lines, each of which is coupling with corresponding memory cells; and

a sequencer for controlling accessing to the nonvolatile memory cells in accordance with the instruction,

wherein the sequencer performs an erase operation in response to an erase instruction that the threshold voltage of all of the nonvolatile memory cells coupled with a selected word line move over a first boundary voltage indicating an erase state,

wherein the sequencer is capable of performing a first program operation in response to a program instruction accompanied with program data, a quantity of which is the same as the storage quantity of all of the nonvolatile memory cells coupled with one word line, that the threshold voltage of all of the nonvolatile memory cells coupled with a selected word line move over a second boundary voltage indicating a program state from the erase state, and

wherein the sequencer is capable of performing a second program operation in response to the program instruction accompanied with program data, a quantity of which is less than the storage quantity of all of the nonvolatile memory cells coupled with one word line, in which the threshold voltage of first ones of the nonvolatile memory cells coupled with the selected word line move over the second boundary voltage indicating the program state from the erase state when second ones of the nonvolatile memory cells coupled with the selected word line, which is the same word line coupled with the first ones of the nonvolatile memory cells, have been in the program state.

6. A nonvolatile memory according to claim 5, further comprising:

terminals coupling with the control device for receiving the instruction; and

a command register for temporarily storing the instruction.

7. A nonvolatile memory according to claim 5,

wherein the sequencer performs a read operation in the erase operation for checking whether the threshold voltage of all of the nonvolatile memory cells coupled with the selected word line have moved over the first boundary voltage or not.

8. A nonvolatile memory according to claim 5,

wherein the sequencer performs a read operation in the program operation for checking whether the threshold voltage of the first ones of the nonvolatile memory cells coupled with the selected word line have moved over the second boundary voltage or not.