Memory system, memory device, and output data strobe signal generating method

• US 8,004,911 B2
• Filed: 04/29/2010
• Issued: 08/23/2011
• Est. Priority Date: 10/19/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Ho-Young, Park, Kwang-Il, Jang, Seong-Jin
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US12/662,720
• Publication Number:
  US 20100284231A1
• Time in Patent Office: 481 Days
• Field of Search: 365/193, 365/233, 365/194, 365/191, 365/189.06, 365/189.03, 365/189.07, 365/185.22, 365/185.2, 365/212
• US Class Current: 365/193
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

Claims

1. A memory system, comprising:

a first memory device, and a second memory device,

wherein the first memory device comprises

a command decoder configured to detect a read command of the first memory device and a read command of the second memory device, generate a first read signal for the first memory device, a second read signal which is a synchronized signal of the read command of the second memory device and a mode setting signal;

a mode setting portion configured to generate a burst length information and a CAS latency information in response to the mode setting signal;

a preamble cycle calculator configured to calculate a preamble cycle number in response to the first read signal, the second read signal and the burst length information; and

an output data strobe signal generator configured to generate the output data strobe signal in response to the burst length information, the CAS latency information and the preamble cycle number.

2. The memory system of claim 1, wherein the preamble cycle number is calculated by subtracting a clock cycle number of the burst length information from a clock cycle number between the first and second read signal.

3. A semiconductor memory device, comprising:

a command decoder configured to generate a first read signal, a second read signal, and a mode setting signal;

a mode setting portion configured to generate a burst length information and a CAS latency information in response to the mode setting signal;

a preamble cycle calculator configured to calculate a preamble cycle number, and

an output data strobe signal generator configured to generate the output data strobe signal in response to the burst length information, the CAS latency information and the preamble cycle number.

4. The device of claim 3, wherein the preamble cycle number is calculated based on the first read signal, the second read signal and the burst length information.

5. The device of claim 3, wherein the preamble cycle number is calculated by subtracting a clock cycle number of the burst length information from a clock cycle number between the first read signal and the second read signal.

6. A strobe signal generative method comprising:

setting a burst length information, a CAS latency information and a preamble clock cycle number of the data strobe signal;

receiving a read command signal of a first memory device;

receiving a read command signal of a second memory device; and

calculating a clock cycle number of the data strobe preamble signal by subtracting a clock cycle number of the burst length information from a clock cycle number between the read command signal of a first memory device and the read command signal of a second memory device.

7. A data strobe preamble signal generating method comprising:

setting a burst length information and a CAS latency information;

receiving a first read command signal of a memory device;

receiving a second read command signal of the memory device; and

calculating a clock cycle number of the data strobe preamble signal by subtracting a clock cycle number of the burst length information from a clock cycle number between the first read command signal and the second read command signal of the memory device.

8. A semiconductor memory device having a preamble clock cycle number of an output data strobe signal set as at least 2 clock cycles, comprising:

a command decoder configured to generate a first read signal, a second read signal and a mode setting signal;

a mode setting portion configured to generate a burst length information and a CAS latency information in response to the mode setting signal;

a preamble cycle calculator configure to calculate a preamble cycle number; and

the output data strobe signal generate configure to generate the output data strobe signal in response to the burst length information the CAS latency information and the preamble cycle number.