Transmitter and receiver using forward clock overlaying link information
First Claim
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1. A transceiver, comprising:
- a clock signal line;
data signal lines;
a transmitter that transmits a clock signal to the clock signal line and respectively transmits data signals to the data signal lines; and
a receiver that receives the clock signal and the data signals which are transmitted through the clock signal line and the data signal lines,wherein the transmitter includes an encoder circuit that transmits a bit sequence obtained by encoding link information including byte alignment information to the clock signal line, andwherein the receiver includes a clock and data recovery circuit that extracts a clock component from the signal that is received from the clock signal line and recovers the bit sequence from the signal that is received from the clock signal line by using the extracted clock component, a decoder circuit that decodes the recovered bit sequence to reproduce the link information, a first deskew circuit that adjusts a skew among the signals received from the respective data signal lines in a time range lower than one bit on the basis of the clock component, a plurality of demultiplexers respectively converting the recovered bit sequence and outputs of the first deskew circuit into parallel data based on byte alignment information extracted from the reproduced link information, and a second deskew circuit that eliminates misalignments in the parallel data due to a bitwise skew remaining among the outputs of the first deskew circuit.
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Accused Products
Abstract
A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
17 Citations
12 Claims
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1. A transceiver, comprising:
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a clock signal line; data signal lines; a transmitter that transmits a clock signal to the clock signal line and respectively transmits data signals to the data signal lines; and a receiver that receives the clock signal and the data signals which are transmitted through the clock signal line and the data signal lines, wherein the transmitter includes an encoder circuit that transmits a bit sequence obtained by encoding link information including byte alignment information to the clock signal line, and wherein the receiver includes a clock and data recovery circuit that extracts a clock component from the signal that is received from the clock signal line and recovers the bit sequence from the signal that is received from the clock signal line by using the extracted clock component, a decoder circuit that decodes the recovered bit sequence to reproduce the link information, a first deskew circuit that adjusts a skew among the signals received from the respective data signal lines in a time range lower than one bit on the basis of the clock component, a plurality of demultiplexers respectively converting the recovered bit sequence and outputs of the first deskew circuit into parallel data based on byte alignment information extracted from the reproduced link information, and a second deskew circuit that eliminates misalignments in the parallel data due to a bitwise skew remaining among the outputs of the first deskew circuit. - View Dependent Claims (2, 3, 4)
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5. A transmitter that transmits a clock signal and data signals by the aid of a clock signal line and data signal lines, the transmitter comprising:
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a plurality of multiplexers, each being provided with n-bit parallel signals indicative of data to be transmitted from an upper layer and converting the parallel signals into a serial bit sequence; a plurality of transmitting buffers transmitting outputs of the multiplexers to the data lines respectively; an encoder circuit that encodes link information into transmission code; an additional multiplexer converting the transmission code into a serial bit string having a clock signal component indicative of transitions between bits of said outputs of the multiplexers; and an additional transmitting buffer transmitting output of the additional multiplexer to the clock signal line, wherein said transmission code includes a particular pattern indicative of byte alignment of outputs of the plurality of multiplexers and the additional multiplexer. - View Dependent Claims (6, 7, 8)
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9. A receiver that receives a clock signal and data signals which are transmitted from a transmitter by the aid of a clock signal line and data signal lines, the receiver comprising:
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clock and data recovery circuit that extracts a clock component from a signal that is received from the clock signal line and recovers a bit sequence from the signal that is received from the clock signal line by using the extracted clock component; a decoder circuit that decodes parallel data derived from the recovered bit sequence to reproduce link information; a first deskew circuit that adjusts a skew among the signals received from the respective data signal lines in a time range lower than one bit on the basis of the clock component; a plurality of demultiplexers respectively converting the recovered bit sequence and outputs of the first deskew circuit into parallel data based on byte alignment information extracted from the reproduced link information; and a second deskew circuit that eliminates misalignments in the parallel data due to a bitwise skew remaining among the outputs of the first deskew circuit. - View Dependent Claims (10, 11, 12)
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsYamashita, Hiroki, Saito, Tatsuya, Chujo, Norio, Toyoda, Hidehiro
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Primary Examiner(s)Liu; Shuwang
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Assistant Examiner(s)Singh; Hirdepal
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Application NumberUS11/826,300Publication NumberTime in Patent Office1,502 DaysField of Search375/219, 375/220, 375/222, 375/243, 375/254, 375/259, 375/292, 375/295, 375/299, 375/316, 375/306, 375342-344, 375/135, 375/150, 375/211, 375/223, 375/242, 375/272, 375/297, 375/327, 375/346, 375/350, 713/400, 713/500, 713/513US Class Current375/219CPC Class CodesH04L 7/0337 Selecting between two or mo...
