Programming error correction code into a solid state memory device with varying bits per cell

• US 8,006,166 B2
• Filed: 06/12/2007
• Issued: 08/23/2011
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hoei, Jung S., Roohparvar, Frankie F., Sarin, Vishal
• Primary Examiner(s): Tabone, Jr.; John J
• Application Number:
  US11/761,608
• Publication Number:
  US 20080313493A1
• Time in Patent Office: 1,533 Days
• Field of Search: 714/768, 714/718, 714/764, 714/774, 714/799, 365/185.09, 365/201
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators

Abstract

Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Claims

1. A method for programming error correction code, at varying bits per cell, into a solid state memory device comprising a memory array, the method comprising:

determining a first reliability level, at a bit level, for a memory area in which a block of data is stored;

storing the error correction code, having a second reliability level, in the memory area and at the bit level if the first reliability level is at least substantially equal to the second reliability level; and

writing the error correction code to another area of the memory array if the first reliability level is less than the second reliability level.

2. The method of claim 1 and further including:

decreasing the bit level to a reduced bit level in order to increase the first reliability level to a third reliability level; and

storing the error correction code with the data block, at the reduced bit level, if the third reliability level is at least equal to the second reliability level.

3. The method of claim 1 and further including storing metadata with the error correction code.

4. The method of claim 1 wherein determining the first reliability level comprises reading a table from memory comprising a calibrated reliability level for each of a plurality of areas of the memory array in relation to a bit level for each of the plurality of areas of the memory array.

5. The method of claim 1 wherein determining the first reliability level comprises writing data, at a plurality of different bit levels, to each of a plurality of memory areas of the memory array in order to find a first memory area of the plurality of memory areas in which the first reliability level is at least equal to the second reliability level at a first of the plurality of different bit levels.

6. The method of claim 5 and further including writing the data to the first memory area at the first bit level.

7. A method for programming error correction code for a data block into a solid state memory device having a memory array, the method comprising:

generating a plurality of reliability levels, each with a corresponding bit level, for a plurality of representative cells of the memory array;

determining a desired reliability level for the error correction code;

determining an area of the memory array comprising the representative cell having the reliability level of the plurality of reliability levels that is at least substantially equal to the desired reliability level;

writing the error correction code to the area of the memory array using the corresponding bit level; and

linking the error code to the data block.

8. The method of claim 7 wherein generating the plurality of bit levels is accomplished at initial power-up of the memory device.

9. The method of claim 7 wherein linking the error correction code to the data block comprises linking an address of the error correction code to an address of the data block such that an access to the data block comprises an access to the error correction code.

10. The method of claim 7 wherein generating the plurality of reliability levels comprises:

writing a first voltage to a first cell;

programming a plurality of cells substantially adjacent to the first cell;

reading a threshold voltage of the first cell in response to the programming of the plurality of substantially adjacent cells; and

generating an indication of a reliability level of the first cell to remain at the first voltage.

11. The method of claim 10 and further including programming the plurality of cells substantially adjacent to the first cell along a same word line of the memory array.

12. The method of claim 10 and further including programming the plurality of cells substantially adjacent to the first cell along a same bit line of the memory array.

13. A method for programming received data into a data block of a non-volatile memory array, the method comprising:

determining if the received data is error correction code;

writing received data that is not error correction code to the data block at a bit level of at least two bits per cell;

determining a desired reliability level for the received data that is error correction code;

determining a reliability level for the data block at a first bit level;

if the reliability level for the data block is at least substantially equal to the desired reliability level, writing the error correction code to the data block at the first bit level;

if the reliability level for the data block is less than the desired reliability level, decreasing the first bit level to a decreased bit level in order to increase the reliability level to an increased reliability level; and

if the increased reliability level is at least substantially equal to the desired reliability level, writing the correction code to the data block at the decreased bit level.

14. The method of claim 13 and further including:

if the increased reliability level is less than the desired reliability level, determine a separate area of memory array from the data block having a reliability level that is at least substantially equal to the desired reliability level at a second bit level; and

writing the error correction code to the separate area of memory at the second bit level.

15. A solid state memory device, comprising:

an array of non-volatile memory cells having columns of memory cells coupled to bit lines and rows of memory cells coupled to word lines; and

circuitry for control and access of the array of non-volatile memory cells wherein the circuitry for control and access is adapted to program error correction code and metadata for a block of data by determining a desired reliability level for the error correction code and metadata, determining a memory area reliability level, at a bit level, for the memory area of the memory array in which the block of data is stored, storing the error correction code and metadata with the block of data and at the bit level if the memory area reliability level is at least substantially equal to the desired reliability level, and writing the error correction code and metadata to another area of the memory array if the memory area reliability level is less than the desired reliability level.

16. The solid state memory device of claim 15 wherein the circuitry for control and access is further adapted to read analog data signals from the memory cells being programmed and to generate digital threshold voltage signals indicative of the read analog data signals.

17. The solid state memory device of claim 15 wherein the circuitry for control and access of the array of non-volatile memory cells comprises circuitry to receive a digital data signal indicative of a programmed memory state and to convert the digital data signal to an analog data signal indicative of a threshold voltage of the programmed memory state.

18. The solid state memory device of claim 15 wherein the array of non-volatile memory cells is organized in a NAND architecture.

19. The solid state memory device of claim 15 wherein the circuitry for control and access is further adapted to program a first threshold voltage to a first cell, program a plurality of cells substantially adjacent to the first cell with a second threshold voltage, read the first cell to determine an effect on the first threshold voltage by the second threshold voltage, and generate an indication of a reliability level of the first cell in response to the effect on the first threshold voltage.

20. The solid state memory device of claim 15 wherein the memory area reliability level at the bit level is a first logic indication when the memory area retains data at the bit level and a second logic indication when the memory area cannot retain data at the bit level.