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Programming error correction code into a solid state memory device with varying bits per cell

  • US 8,006,166 B2
  • Filed: 06/12/2007
  • Issued: 08/23/2011
  • Est. Priority Date: 06/12/2007
  • Status: Active Grant
First Claim
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1. A method for programming error correction code, at varying bits per cell, into a solid state memory device comprising a memory array, the method comprising:

  • determining a first reliability level, at a bit level, for a memory area in which a block of data is stored;

    storing the error correction code, having a second reliability level, in the memory area and at the bit level if the first reliability level is at least substantially equal to the second reliability level; and

    writing the error correction code to another area of the memory array if the first reliability level is less than the second reliability level.

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