Dynamic push for topological routing of semiconductor packages
First Claim
1. A computer-implemented method for routing topological interconnections for a package, the method comprising:
- receiving, using one or more processors associated with one or more computer systems, information associated with a chip;
determining an escape routing of a bump array for the chip, the escape routing indicative of a set of I/Os along a set of escape boundaries;
determining a set of obstructions on a set of package layers;
determining a scale of via staggering pitches on the set of package layers;
for each build-up layer in the set of package layers, from a top layer to a bottom layer;
performing a topologically planar routing of each I/O in the set of I/Os to a location substantially vertical to a center of a corresponding ball, wherein at least a first net is dynamically pushed in response to the topologically planar routing of a second net, andtransferring a stopping point associated with an I/O for a failed net to another build-up layer by stack vias;
assigning vias for one or more successfully routed nets;
analyzing a congestion associated with each build-up layer to generate a congestion map; and
generating, with the one or more processors associated with the one or more computer systems, information indicative of a set of topological interconnections, the congestion map, and a set of fail-routed nets and storing the information in a storage device associated with the one or more computers systems.
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Accused Products
Abstract
Techniques are disclosed for performing topologically planar routing of System in Packages (SiPs). A routing graph can be represented by a particle-insertion-based constraint Delaunay triangulation (PCDT) and its dual. A dynamic search routing may be performed using a DS* routing algorithm to determine the shortest path on the dual graph between a start point and an end point. Based on a dynamic pushing technique, net ordering problems may be solved. A first wire can be topologically routed. Dynamic search routing of a second wire may be performed. The first wire may be pushed or detoured in response to the dynamic searching routing of a second wire.
38 Citations
32 Claims
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1. A computer-implemented method for routing topological interconnections for a package, the method comprising:
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receiving, using one or more processors associated with one or more computer systems, information associated with a chip; determining an escape routing of a bump array for the chip, the escape routing indicative of a set of I/Os along a set of escape boundaries; determining a set of obstructions on a set of package layers; determining a scale of via staggering pitches on the set of package layers; for each build-up layer in the set of package layers, from a top layer to a bottom layer; performing a topologically planar routing of each I/O in the set of I/Os to a location substantially vertical to a center of a corresponding ball, wherein at least a first net is dynamically pushed in response to the topologically planar routing of a second net, and transferring a stopping point associated with an I/O for a failed net to another build-up layer by stack vias; assigning vias for one or more successfully routed nets; analyzing a congestion associated with each build-up layer to generate a congestion map; and generating, with the one or more processors associated with the one or more computer systems, information indicative of a set of topological interconnections, the congestion map, and a set of fail-routed nets and storing the information in a storage device associated with the one or more computers systems. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer-implemented method for routing topological interconnections for a package, the method comprising:
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receiving, using one or more processors associated with one or more computer systems, information associated with a build-up layer of the package; generating a constraint Delaunay graph and a corresponding dual constraint Delaunay graph for the build-up layer; determining a routing order associated with a set of nets for the build-up layer to generate a first set of ordered nets; determining a set of routing control parameters; performing a dynamic search routing using the dual constraint Delaunay graph and the set of routing control parameters to determine a topological planar routing for each net in the first set of ordered nets, wherein at least one net in the first set of ordered nets detours another net in the first set of ordered nets; and generating, with the one or more processors associated with the one or more computer system, information indicative of the topological planar routing for each net in the first set of ordered nets and storing the information in a storage device associated with the one or more computers systems. - View Dependent Claims (14, 15, 16, 17)
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18. A non-transitory computer readable medium configured to store a set of code modules which when executed by a processor of a computer system become operational with the processor for routing topological interconnections of a package, the non-transitory computer readable medium comprising:
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code for receiving information associated with a chip; code for determining an escape routing of a bump array for the chip, the escape routing indicative of a set of I/Os along a set of escape boundaries; code for determining a set of obstructions on a set of package layers; code for determining a scale of via staggering pitches on the set of package layers; code for, for each build-up layer in the set of package layers, from a top layer to a bottom layer; performing a topologically planar routing of each I/O in the set of I/Os to a location substantially vertical to a center of a corresponding ball, wherein at least a first net is dynamically pushed in response to the topologically planar routing of a second net, and transferring a stopping point associated with an I/O for a failed net to another build-up layer by stack vias; code for assigning vias for one or more successfully routed nets; code for analyzing a congestion associated with each build-up layer to generate a congestion map; and code for generating information indicative of a set of topological interconnections, the congestion map, and a set of fail-routed nets. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A non-transitory computer readable medium configured to store a set of code modules which when executed by a processor of a computer system become operational with the processor for routing topological interconnections of a package, the non-transitory computer readable medium comprising:
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code for receiving information associated with a build-up layer of the package; code for generating a constraint Delaunay graph and a corresponding dual constraint Delaunay graph for the build-up layer; code for determining a routing order associated with a set of nets for the build-up layer to generate a first set of ordered nets; code for determining a set of routing control parameters; and code for performing a dynamic search routing using the dual constraint Delaunay graph and the set of routing control parameters to determine topological planar routing for each net in the first set of ordered nets, wherein at least one net in the first set of ordered nets detours another net in the first set of ordered nets.
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25. A system for routing topological interconnections of a package, the system comprising:
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a processor; and a memory coupled to the processor, the memory configured to store a set of instructions which when executed by the processor cause the processor to; receive information associated with a chip; determine an escape routing of a bump array for the chip, the escape routing indicative of a set of I/Os along a set of escape boundaries; determine a set of obstructions on a set of package layers; determine a scale of via staggering pitches on the set of package layers; for each build-up layer in the set of package layers, from a top layer to a bottom layer; perform a topologically planar routing of each I/O in the set of I/Os to a location substantially vertical to a center of a corresponding ball, wherein at least a first net is dynamically pushed in response to the topologically planar routing of a second net, and transfer a stopping point associated with an I/O for a failed net to another build-up layer by stack vias; assign vias for one or more successfully routed nets; analyze a congestion associated with each build-up layer to generate a congestion map; and generate information indicative of a set of topological interconnections, the congestion map, and a set of fail-routed nets. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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32. A system for routing topological interconnections of a package, the system comprising:
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a processor; and a memory coupled to the processor, the memory configured to store a set of instructions which when executed by the processor cause the processor to; receive information associated with a build-up layer of the package; generate a constraint Delaunay graph and a corresponding dual constraint Delaunay graph for the build-up layer; determine a routing order associated with a set of nets for the build-up layer to generate a first set of ordered nets; determine a set of routing control parameters; and perform a dynamic search routing using the dual constraint Delaunay graph and the set of routing control parameters to determine a topological planar routing for each net in the first set of ordered nets, wherein at least one net in the first set of ordered nets detours another net in the first set of ordered nets.
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Specification